Abstract: Apparatuses, systems, and techniques to access one or more non-uniform memory access (NUMA) nodes. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause one or more NUMA nodes or one or more physical addresses allocated to one or more graphics processing units (GPUs) to be accessed based, at least in part, on one or more indications within the API.

Abstract: Apparatuses, systems, and techniques to indicate whether one or more storages correspond to one or more non-uniform memory access (NUMA) storages. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to indicate whether one or more storages indicated by one or more users of the API corresponds to one or more NUMA storages or one or more graphics processing unit (GPU) storages.

Abstract: Apparatuses, systems, and techniques to cause information to be read from one or more non-uniform memory access (NUMA) storages. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information to be read from one or more NUMA storages or one or more graphics processor unit (GPU) physical storages based, at least in part, on one or more indicators to be indicated by one or more users of the API.

Abstract: Apparatuses, systems, and techniques to store information within one or more non-uniform memory access (NUMA) storages. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information to be stored within one or more NUMA storages or one or more graphics processor unit (GPU) physical storages based, at least in part, on one or more indicators to be indicated by one or more users of the API.

Abstract: Apparatuses, systems, and techniques to allocate processor memory. In at least one embodiment, an application programming interface is used to execute instructions to asynchronously allocate memory locations to processors.

Abstract: Apparatuses, systems, and techniques to execute software programs. In at least one embodiment, an application programming interface (API) is performed to cause context information to be updated to indicate whether one or more memory operations to be performed are dependent on one or more other memory operations.

Abstract: Apparatuses, systems, and techniques to execute software programs. In at least one embodiment, an application programming interface (API) is performed to cause an indication to be stored of whether one or more memory operations to be performed are dependent on one or more other memory operations.

Abstract: Apparatuses, systems, and techniques to execute software programs. In at least one embodiment, an application programming interface (API) is performed to cause an indication to be read from a primary context data structure of whether one or more memory operations to be performed are dependent on one or more other memory operations.

Abstract: Apparatuses, systems, and techniques to execute software programs. In at least one embodiment, an application programming interface (API) is performed to cause an indication to be read of whether one or more memory operations to be performed are dependent on one or more other memory operations.

Abstract: Apparatuses, systems, and techniques to execute software programs. In at least one embodiment, an application programming interface (API) is performed to cause an indication to be stored within a primary context data structure of whether one or more memory operations to be performed are dependent on one or more other memory operations.

Abstract: Apparatuses, systems, and techniques to allocate processor memory. In at least one embodiment, an application programming interface is used to execute instructions to asynchronously allocate memory locations to processors.

Abstract: Apparatuses, systems, and techniques to limit memory during execution of one or more kernels and/or thread groups during PPU execution. In at least one embodiment, a process indicates a memory limit for one or more kernels and/or thread groups to a parallel processing library, and said parallel processing library restricts memory allocation for said one or more kernels and/or thread groups according to said memory limit.

Abstract: Apparatuses, systems, and techniques to allocate processor memory. In at least one embodiment, an application programming interface is used to execute instructions to asynchronously deallocate memory locations from processors.

Abstract: Apparatuses, systems, and techniques to limit one or more computational resources to be used to execute one or more CUDA programs. In at least one embodiment, a user indicates to an application programming interface (API) one or more global data values to indicate a limit on one or more computational resources of a parallel processing unit (PPU) and said API enforces said limit on one or more computational resources during execution of one or more CUDA programs.

Abstract: Apparatuses, systems, and techniques to generate one or more graph code nodes to deallocate memory. In at least one embodiment, one or more graph code nodes to deallocate memory are generated, based on, for example, CUDA or other parallel computing platform code.

Abstract: Apparatuses, systems, and techniques to generate one or more graph code nodes to allocate memory. In at least one embodiment, one or more graph code nodes to allocate memory are generated, based on, for example, CUDA or other parallel computing platform code.

Abstract: Apparatuses, systems, and techniques to indicate storage to be compressed. In at least one embodiment, an application programming interface is performed to indicate storage to store information to be compressed.

Abstract: Apparatuses, systems, and techniques to execute one or more application programming interface (API) functions to facilitate parallel computing. In at least one embodiment, one or more APIs are to indicate information about one or more storage locations using various novel techniques described herein.

Abstract: Apparatuses, systems, and techniques to execute one or more application programming interface (API) functions to facilitate parallel computing. In at least one embodiment, one or more APIs are to indicate one or more storage locations using various novel techniques described herein.

Abstract: Apparatuses, systems, and techniques to execute one or more application programming interface (API) functions to facilitate parallel computing. In at least one embodiment, one or more APIs are to indicate whether one or more storage locations can be shared during performance of software using various novel techniques described herein.