Abstract: A process and apparatus for testing wide word memory parts (618-624), sixteen data I/O leads per part, uses two stages of relays (610, 612 and 614) to connect the memory parts to sixteen test receivers (Ra, Rb, Rc and Rd). When the memory parts are in a normal operating mode or non-DFT mode, the relays connect all sixteen data I/O leads of each memory part to the sixteen test receivers, one memory part at a time. When the memory parts are in the DFT mode, the relays connect all the active DFT data I/O leads (0-3) to the receivers. A test performance board can carry one or more modules of memory parts with each module containing plural sockets for retaining the memory parts and one or more stages of relays.

Abstract: In accordance with a broad aspect of the invention, a system is presented for parametrically and functionally testing integrated circuit devices in parallel. At least one integrated circuit device receiving channel is provided for defining a plurality of integrated circuit device test stations therealong, and means are provided for delivering parametric and functional test signals at least functionally in parallel to each of the integrated circuit device test stations. Means are provided at each test station for selectively engaging the integrated circuit devices to apply the parametric and functional test signals to the integrated circuit device at that station, and to selectively isolate the device from the test signals. Means are provided for receiving an output from each test location in response to the test signals, and means for determining from the output the parameters of each tested integrated circuit device.