Abstract: A time delay circuit in a battery protection chip for an internal time delay or external time delay selection is disclosed. The protection chip has a selective pin for choosing the internal time delay while the selective pin is floated or the external time delay while the selective pin is connected with a capacitor. The time delay circuit is composed of a charge-discharge circuit, a D flip-flop, a RS latch, a NOR gate, and a 2 to 1 multiplexer (MUX 2:1). According to an embodiment, if the selective pin is floated, the outputs of the D flip-flop, and the RS latch will make MUX 2:1 choose an output signal of the NOR gate having input signals of an internal delay signal and input signal. On the other hand, if the selective pin is connected with an external capacitor having an external capacitance of more than 250 pF, the output signal of the D flip-flop, and the RS latch will make MUX 2:1 choose an output of the charge-discharge circuit but ignore the internal delay signal.

Abstract: A wake-up circuit includes a counter, a register circuit, a first logic circuit, an oscillator, a flip flop, and a second logic circuit. The wake-up circuit receives a standby signal to stop the oscillator working and to wait for the wake-up signal to reactivate the oscillator again. When the duration of the wake-up signal is shorter than an expected time of the counter, the oscillator stops working again and re-enters the saving mode. When the duration of the wake-up signal is longer than the expected time of the counter, the counter controls the flip flop to output a preset signal to the register circuit, and as a result that keeps the oscillator working even after the wake-up signal is removed by the first logic circuit operating, and then the second logic circuit operates with flip-flop to set the counter returning to a normal state to wait for a next standby signal to feed in.

Abstract: A time delay circuit in a battery protection chip for an internal time delay or external time delay selection is disclosed. The protection chip has a selective pin for choosing the internal time delay while the selective pin is floated or the external time delay while the selective pin is connected with a capacitor. The time delay circuit is composed of charge-discharge circuit, D flip-flop, RS latch, NOR gate, a 2 to 1 multiplexer (MUX 2:1). According to an embodiment, if the selective pin is floated, the outputs of the D flip-flop, and the RS latch will make MUX 2:1 to choose an output signal of the NOR gate having input signals of an internal delay signal and input signal. On the other hand, if the selective pin is connected with an eternal capacitor having an eternal capacitor more than 250 pF, the output signal of the D flip-flop, RS latch will make MUX 2:1 to choose an output of the charge-discharge circuit but ignores the internal delay signal.

Abstract: A trimming fuse circuit with a latch is disclosed. The trimming fuse circuit includes: a first CMOS transistor having a first PMOS and a second NMOS, wherein said first PMOS has a size smaller than that of said first NMOS; a second CMOS transistor having a second PMOS and a second NMOS, wherein said second PMOS has a size larger than that of said second NMOS, and still an input terminal of said second CMOS is cross-coupled with an output terminal of said first CMOS, furthermore, an output terminal of said first CMOS is cross-coupled with an input terminal of said second CMOS; and a fuse connected in between said input terminal of said first CMOS transistor and ground; thus, outputting an voltage high control signal from said output terminal of said first CMOS while said voltage high fuse is not burned-out; and outputting an voltage low control signal voltage low whiles said fuse is burned-out.

Abstract: A wake-up circuit includes a counter, a register circuit, a first logic circuit, an oscillator, a flip flop, and a second logic circuit. The wake-up circuit receives a standby signal to stop the oscillator working and to wait for the wake-up signal to reactivate the oscillator again. When the duration of the wake-up signal is shorter than an expected time of the counter, the oscillator stops working again and re-enters the saving mode. When the duration of the wake-up signal is longer than the expected time of the counter, the counter controls the flip flop to output a preset signal to the register circuit, and as a result that keeps the oscillator working even after the wake-up signal is removed by the first logic circuit operating, and then the second logic circuit operates with flip-flop to set the counter returning to a normal state to wait for a next standby signal to feed in.