Abstract: Aspects of a method and system for hash table based routing via prefix transformation are provided. Aspects of the invention may enable translating one or more network addresses as a coefficient set of a polynomial, and routing data in a network based on a quotient and a remainder derived from the coefficient set. In this regard, the quotient and the remainder may be calculated via modulo 2 division of the polynomial by a primitive generator polynomial. In one example, the remainder may be calculated with the aid of a remainder table. The primitive generator polynomial may be x16+x8+x6+x5+x4+x2+1. Additionally, entries in one or more hash tables may comprise a calculated quotient and may be indexed by a calculated remainder. In this manner, the hash tables may be accessed to determine a longest prefix match for the one or more network addresses. The hash tables may comprise 2deg(g(x)) sets, where deg(g(x)) is the degree of the primitive generator polynomial.

Abstract: Methods, systems and computer program products to implement hardware memory locks are described herein. A system to implement hardware memory locks is provided. The system comprises an off-chip memory coupled to a SOC unit that includes a controller and an on-chip memory. Upon receiving a request from a requester to access a first memory location in the off-chip memory, the controller is enabled to grant access to modify the first memory location based on an entry stored in a second memory location of the on-chip memory. In an embodiment, the on-chip memory is Static Random Access Memory (SRAM) and the off-chip memory is Random Access Memory (RAM).

Abstract: A memory system is provided comprising a memory controller, a level 1 (L1) cache including L1 tag memory and L1 data memory, a level 2 (L2) cache coupled to the L1 cache, the L2 cache including L2 tag memory having a plurality of L2 tag entries and a L2 data memory having a plurality of L2 data entries. The L2 tag entries are more than the L2 data entries. In response to receiving a tag and an associated data, if L2 tag entries having corresponding L2 data entries are unavailable and if a first tag in a first L2 tag entry with an associated first data in a first L2 data entry has a more recent or duplicate value of the first data in the L1 data memory, the memory controller moves the first tag to a second L2 tag entry that does not have a corresponding L2 data entry, vacates the first L2 tag entry and the first L2 data entry and stores the received tag in the first L2 tag entry and the received data in the first L2 data entry.

Abstract: Methods, systems and computer program products for global address space management are described herein. A System on Chip (SOC) unit configured for a global address space is provided. The SOC includes an on-chip memory, a first controller and a second controller. The first controller is enabled to decode addresses that map to memory locations in the on-chip memory and the second controller is enabled to decode addresses that map to memory locations in an off-chip memory.

Abstract: Methods, systems and computer program products to implement hardware memory locks are described herein. A system to implement hardware memory locks is provided. The system comprises an off-chip memory coupled to a System-On-a-Chip(SOC) unit that includes a controller and an on-chip memory. Upon receiving a request from a requester to access a first memory location in the off-chip memory, the controller is enabled to grant access to modify the first memory location based on an entry stored in a second memory location of the on-chip memory. In an embodiment, the on-chip memory is Static Random Access Memory (SRAM) and the off-chip memory is Random Access Memory (RAM).

Abstract: Methods, systems and computer program products to maintain cache coherency, in a System On Chip (SOC) which is part of a distributed shared memory system are described. A local SOC unit that includes a local controller and an on-chip memory is provided. In response to receiving a request from a remote controller of a remote SOC to access a memory location, the local controller determines whether the local SOC has exclusive ownership of the requested memory location, sends data from the memory location if the local SOC has exclusive ownership of the memory location and stores an entry in the on-chip memory that identifies the remote SOC as having requested data from the memory location. The entry specifies whether the request from the remote SOC is for exclusive ownership of the memory location. The entry also includes a field that identifies the remote SOC as the requester. The requested memory location may be external or internal to the local SOC unit.

Abstract: The invention relates to insertion and removal of MPA markers and RDMA CRCs in RDMA data streams, after determining the locations for these fields. An embodiment of the invention comprises a host interface, a transmit interface connected to the host interface, and a processor interface connected to both transmit and host interfaces. The host interface operates under the direction of commands received from the processor interface when processing inbound RDMA data. The host interface calculates the location of marker locations and removes the markers. The transmit interface operates under the direction of commands received from the processor interface when processing outbound RDMA data. The transmit interface calculates the positions in the outbound data where markers are to be inserted. The transmit interface then places the markers accordingly.

Abstract: A method for processing data is disclosed and may include performing by one or more processors and/or circuits on a chip that handles a plurality of networking protocols, receiving data for one or more network connections corresponding to one or more of the plurality of networking protocols. The chip may be configured for handling the received data based on whether the one or more of the plurality of networking protocols associated with the received data includes transmission control protocol and/or remote direct memory access protocol. The received data may be processed based on the configuration. At least one RDMA marker may be removed from the received data when the received data includes the RDMA protocol, and/or the received data is processed based on a transmission control protocol session identification within the received data.

Abstract: Aspects of a method and system for efficient and cache-friendly TCP session lookup operations based on canonicalization tags are presented. Aspects of the method may include searching a plurality of tag fields, retrieved via a single memory read operation, to locate a reference to a control block that includes context information for a communication session. Aspects of the system may include a processor that searches a plurality of tag fields, retrieved via a single memory read operation, to locate a reference to a control block that includes context information for a communication session.

Abstract: Methods, systems and computer program products for global address space management are described herein. A System-On-a-Chip (SOC) unit configured for a global address space is provided. The SOC includes an on-chip memory, a first controller and a second controller. The first controller is enabled to decode addresses that map to memory locations in the on-chip memory and the second controller is enabled to decode addresses that map to memory locations in an off-chip memory.

Abstract: Methods, systems and computer program products to maintain cache coherency in a System-On-a-Chip (SOC) which is part of a distributed shared memory system are described. A local SOC unit that includes a local controller and an on-chip memory is provided. In response to receiving a request from a remote controller of a remote SOC to access a memory location, the local controller determines whether the local SOC has exclusive ownership of the requested memory location, sends data from the memory location if the local SOC has exclusive ownership of the memory location and stores an entry in the on-chip memory that identifies the remote SOC as having requested data from the memory location. The entry specifies whether the request from the remote SOC is for exclusive ownership of the memory location. The entry also includes a field that identifies the remote SOC as the requester. The requested memory location may be external or internal to the local SOC unit.

Abstract: Managing data traffic among three or more bus agents configured in a topological ring can include numbering each bus agent sequentially and injecting messages from the bus agents into the ring during cycles of bus agent activity, where the messages include a binary polarity value and a queue entry value. Messages are received from the ring into two or more receive buffers of a receiving bus agent. The value of the binary polarity value is changed after succeeding N cycles of bus ring activity, where N is the number of bus agents connected to the ring. The received messages are ordered for processing by the receiving bus agent based on at least in part on the polarity value of the messages and the queue entry value of the messages.

Abstract: Certain aspects of a method and system for a system-on-a-chip (SoC) device with integrated support for Ethernet, TCP, iSCSI, RDMA, and network application acceleration are provided. Aspects of the method may include storing on a multifunction host bus adapter (MHBA) chip that handles a plurality of protocols, at least a portion of received data for at least one of a plurality of network connections. The MHBA chip may be configured for handling the received data based on one of the plurality of protocols that is associated with the received data. The received data for the at least one of the plurality of network connections may be processed within the MHBA chip. The one of the plurality of protocols may include an Ethernet protocol, a transmission control protocol (TCP), an Internet protocol (IP), an Internet small computer system interface (iSCSI) protocol, and/or a remote direct memory access (RDMA) protocol.

Abstract: A method of processing network packets can include allocating a first portion of a physical memory device to kernel-space control and allocating a second portion of the physical memory device to direct user-space process control. Network packets can be received from a computer network, and the received network packets can be written to the second portion of the physical memory without writing the received packets to the first portion of the physical memory.

Abstract: The invention relates to insertion and removal of MPA markers and RDMA CRCs in RDMA data streams, after determining the locations for these fields. An embodiment of the invention comprises a host interface, a transmit interface connected to the host interface, and a processor interface connected to both transmit and host interfaces. The host interface operates under the direction of commands received from the processor interface when processing inbound RDMA data. The host interface calculates the location of marker locations and removes the markers. The transmit interface operates under the direction of commands received from the processor interface when processing outbound RDMA data. The transmit interface calculates the positions in the outbound data where markers are to be inserted. The transmit interface them places the markers accordingly.

Abstract: In one aspect, there is provided a method for use by an edge device for establishing a connection with a server to support a full TCP connection between a client and the edge device. The method comprises establishing a full TCP connection with the server using a full TCP socket, allocating a first light TCP socket for supporting a first light TCP connection with the server, associating a first light session ID with the first light TCP connection, sending a first open session message to the server via the full TCP connection with the server, establishing the first light TCP connection with the server via the full TCP connection, associating first data with the first light session ID, and delivering the first data associated with the first light session ID to the server using the first light TCP connection via the full TCP connection.

Abstract: A system includes a first bus segment and a second bus segment. The first bus segment is operatively coupled to one or more first bus agents, where the first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment and the second bus segment, which is separate from the first bus segment, is operatively coupled to one or more second bus agents. The first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment. The system also includes first electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the first bus segment and to write the messages onto the second bus segment and second electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the second bus segment and to write the messages onto the first bus segment.

Abstract: Managing data traffic among three or more bus agents configured in a topological ring includes numbering each bus agent sequentially and injecting messages that include a binary polarity value from the bus agents into the ring in a sequential order according to the numbering of the bus agents during cycles of bus agent activity. Messages from the ring are received into two or more receive buffers of a receiving bus agent, and the value of the binary polarity value is alternated after succeeding cycles of bus ring activity. The received messages are ordered for processing by the receiving bus agent based on the polarity value of the messages and a time at which each message was received.

Abstract: A system includes a first bus segment and a second bus segment. The first bus segment is operatively coupled to one or more first bus agents, where the first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment and the second bus segment, which is separate from the first bus segment, is operatively coupled to one or more second bus agents. The first bus agents are configured for writing messages to the first bus segment and reading messages from the first bus segment. The system also includes first electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the first bus segment and to write the messages onto the second bus segment and second electrical circuitry operably coupled to the first bus segment and the second bus segment and configured to read messages written on the second bus segment and to write the messages onto the first bus segment.

Abstract: Disclosed herein is an apparatus which may comprise a plurality of nodes. In one example embodiment, each of the plurality of nodes may include one or more central processing units (CPUs), a random access memory device, and a parallel link input/output port. The random access memory device may include a local memory address space and a global memory address space. The local memory address space may be accessible to the one or more CPUs of the node that comprises the random access memory device. The global memory address space may be accessible to CPUs of all the nodes. The parallel link input/output port may be configured to send data frames to, and receive data frames from, the global memory address space comprised by the random access memory device(s) of the other nodes.