Patents by Inventor Fong-Yu Yen
Fong-Yu Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180179568Abstract: Lignocellulose is pretreated using solvent with little water footprint. Both a solvent and water are used for saccharification and separating the components of lignocellulose. By adding a small amount of an inorganic acid, lignin is dissolved and hemicellulose is hydrolyzed under appropriate reaction temperature and pressure. Both are dissolved to form liquid phase with solid cellulose residue left. The relative volatility difference between the solvent and water is used to selectively remove more of the solvent. More particularly, drying with air-suction at a relatively low temperature helps remove and recycle the solvent from the cellulose solid residue. Thus, water consumption and the subsequent wastewater treatment can be significantly reduced with little water footprint while achieving the original desired efficiency of enzymatic hydrolysis.Type: ApplicationFiled: December 27, 2016Publication date: June 28, 2018Inventors: Fong-Yu Yen, Hsin-Hung Chen, Gia-Luen Guo, Ming-Feng Jang, Wen-Hua Chen
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Patent number: 8384159Abstract: A semiconductor device is disclosed that includes: a substrate; a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; a second dielectric layer formed over the first dielectric layer and formed of a second high-k material, the second high-k material being different than the first high-k material and selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and a metal gate formed over the second dielectric layer. The first dielectric layer includes ions selected from the group consisting of N, O, and Si.Type: GrantFiled: April 20, 2009Date of Patent: February 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fong-Yu Yen, Cheng-Lung Hung, Peng-Fu Hsu, Vencent S. Chang, Yong-Tian Hou, Jin Ying, Hun-Jan Tao
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Patent number: 8159035Abstract: A semiconductor structure includes a refractory metal silicide layer; a silicon-rich refractory metal silicide layer on the refractory metal silicide layer; and a metal-rich refractory metal silicide layer on the silicon-rich refractory metal silicide layer. The refractory metal silicide layer, the silicon-rich refractory metal silicide layer and the metal-rich refractory metal silicide layer include same refractory metals. The semiconductor structure forms a portion of a gate electrode of a metal-oxide-semiconductor device.Type: GrantFiled: August 17, 2007Date of Patent: April 17, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Donald Y. Chao, Albert Chin, Ping-Fang Hung, Fong-Yu Yen, Kang-Cheng Lin, Kuo-Tai Huang
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Patent number: 7947591Abstract: Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.Type: GrantFiled: April 9, 2008Date of Patent: May 24, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Peng-Fu Hsu, Fong-Yu Yen, Yi-Shien Mor, Huan-Just Lin, Ying Jin, Hun-Jan Tao
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Patent number: 7824990Abstract: A semiconductor structure having a high-k dielectric and its method of manufacture is provided. A method includes forming a first dielectric layer over the substrate, a metal layer over the first dielectric layer, and a second dielectric layer over the metal layer. A method further includes annealing the substrate in an oxidizing ambient until the three layers form a homogenous high-k dielectric layer. Forming the first and second dielectric layers comprises a non-plasma deposition process such atomic layer deposition (ALD), or chemical vapor deposition (CVD). A semiconductor device having a high-k dielectric comprises an amorphous high-k dielectric layer, wherein the amorphous high-k dielectric layer comprises a first oxidized metal and a second oxidized metal. The atomic ratios of all oxidized metals are substantially uniformly within the amorphous high-k dielectric layer.Type: GrantFiled: January 10, 2006Date of Patent: November 2, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Vincent S. Chang, Fong-Yu Yen, Peng-Soon Lim, Jin Ying, Hun-Jan Tao
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Publication number: 20090315125Abstract: A semiconductor device is disclosed that includes: a substrate; a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; a second dielectric layer formed over the first dielectric layer and formed of a second high-k material, the second high-k material being different than the first high-k material and selected from the group consisting of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfTiTaO, HfAlON, and HfZrO; and a metal gate formed over the second dielectric layer. The first dielectric layer includes ions selected from the group consisting of N, O, and Si.Type: ApplicationFiled: April 20, 2009Publication date: December 24, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fong-Yu YEN, Cheng-Lung HUNG, Peng-Fu HSU, Vencent S. CHANG, Yong-Tian HOU, Jin YING, Hun-Jan TAO
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Patent number: 7531399Abstract: A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming a first high-k dielectric layer above the substrate; forming a second dielectric layer of a different high-k material above the first dielectric layer; and forming a gate structure above the second dielectric layer. In yet another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming an interfacial layer above the substrate; forming a first high-k dielectric layer above the interfacial layer; performing a nitridation technique; performing an anneal; forming a second high-k dielectric layer of a different high-k material above the first dielectric layer; and forming a metal gate structure above the second dielectric layer.Type: GrantFiled: September 15, 2006Date of Patent: May 12, 2009Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Fong-Yu Yen, Cheng-Lung Hung, Peng-Fu Hsu, Vencent S. Chang, Yong-Tian Hou, Jin Ying, Hun-Jan Tao
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Publication number: 20080242108Abstract: A method for fabricating a semiconductor device is disclosed. The method includes providing a first chamber and a second chamber. The first chamber and the second chamber are connected by a pressure differential unit, for depositing a metallic film over a substrate in the first chamber, transferring the substrate to the second chamber via the pressure differential unit without exposing the substrate to the ambient environment, and depositing a silicon-containing film on the metallic film in the second chamber.Type: ApplicationFiled: April 2, 2007Publication date: October 2, 2008Inventors: Weng Chang, Fong-Yu Yen, Hun-Jan Tao, Mong-Song Liang
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Publication number: 20080188044Abstract: Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.Type: ApplicationFiled: April 9, 2008Publication date: August 7, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Peng-Fu Hsu, Fong-Yu Yen, Yi-Shien Mor, Huan-Just Lin, Ying Jin, Hun-Jan Tao
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Patent number: 7378713Abstract: Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.Type: GrantFiled: October 25, 2006Date of Patent: May 27, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Peng-Fu Hsu, Fong-Yu Yen, Yi-Shien Mor, Huan-Just Lin, Ying Jin, Hun-Jan Tao
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Publication number: 20080099851Abstract: Semiconductor devices with dual-metal gate structures and fabrication methods thereof. A semiconductor substrate with a first doped region and a second doped region separated by an insulation layer is provided. A first metal gate stack is formed on the first doped region, and a second metal gate stack is formed on the second doped region. A sealing layer is disposed on sidewalls of the first gate stack and the second gate stack. The first metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a first metal layer on the high-k dielectric layer, a metal insertion layer on the first metal layer, a second metal layer on the metal insertion layer, and a polysilicon layer on the second metal layer. The second metal gate stack comprises an interfacial layer, a high-k dielectric layer on the interfacial layer, a second metal layer on the high-k dielectric layer, and a polysilicon layer on the second metal layer.Type: ApplicationFiled: October 25, 2006Publication date: May 1, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Peng-Fu Hsu, Fong-Yu Yen, Yi-Shien Mor, Huan-Just Lin, Ying Jin, Hun-Jan Tao
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Publication number: 20080070395Abstract: A semiconductor device is disclosed that includes: a substrate; a first high-k dielectric layer; a second high-k dielectric layer formed of a different high-k material; and a metal gate. In another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming a first high-k dielectric layer above the substrate; forming a second dielectric layer of a different high-k material above the first dielectric layer; and forming a gate structure above the second dielectric layer. In yet another form, a method of forming a semiconductor device is disclosed that includes: providing a substrate; forming an interfacial layer above the substrate; forming a first high-k dielectric layer above the interfacial layer; performing a nitridation technique; performing an anneal; forming a second high-k dielectric layer of a different high-k material above the first dielectric layer; and forming a metal gate structure above the second dielectric layer.Type: ApplicationFiled: September 15, 2006Publication date: March 20, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Fong-Yu Yen, Cheng-Lung Hung, Peng-Fu Hsu, Vencent S. Chang, Yong-Tian Hou, Jin Ying, Hun-Jan Tao
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Publication number: 20080001237Abstract: Disclosed is a semiconductor device having a substrate, an interfacial layer formed on said substrate, a nitrogen-containing high dielectric constant (high-k) layer formed on said interfacial layer, and a metal electrode on said nitrogen-containing high-k layer. Also disclosed is a method of forming a transistor including forming on a substrate an interfacial layer comprising silicon and oxygen, depositing on the interfacial layer a high-k dielectric material, nitriding the high-k dielectric material, depositing a metal layer on the high-k dielectric material, and patterning the metal layer, the high-k dielectric material, and the interfacial layer to form a gate stack.Type: ApplicationFiled: June 29, 2006Publication date: January 3, 2008Inventors: Vincent S. Chang, Peng-Fu Hsu, Fong-Yu Yen, Yong-Tian Hou, Jin Ying, Hun-Jan Tao
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Publication number: 20070228480Abstract: A CMOS device has PMOS and NMOS transistors with different gate structures overlying a semiconductor device. A first gate structure overlying the PMOS device region has a first gate dielectric layer overlying the semiconductor substrate, and a first gate conductor overlying the first gate dielectric layer. A second gate device region overlying the NMOS device region has a second gate dielectric layer overlying the semiconductor substrate, and a second gate conductor overlying the first gate dielectric layer. The first gate conductor has a silicon-based material layer, and the second gate conductor has a metal-based material layer.Type: ApplicationFiled: April 3, 2006Publication date: October 4, 2007Inventors: Fong-Yu Yen, Peng-Fu Hsu, Ying Jin
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Publication number: 20070128736Abstract: A semiconductor structure having a high-k dielectric and its method of manufacture is provided. A method includes forming a first dielectric layer over the substrate, a metal layer over the first dielectric layer, and a second dielectric layer over the metal layer. A method further includes annealing the substrate in an oxidizing ambient until the three layers form a homogenous high-k dielectric layer. Forming the first and second dielectric layers comprises a non-plasma deposition process such atomic layer deposition (ALD), or chemical vapor deposition (CVD). A semiconductor device having a high-k dielectric comprises an amorphous high-k dielectric layer, wherein the amorphous high-k dielectric layer comprises a first oxidized metal and a second oxidized metal. The atomic ratios of all oxidized metals are substantially uniformly within the amorphous high-k dielectric layer.Type: ApplicationFiled: January 10, 2006Publication date: June 7, 2007Inventors: Vincent Chang, Fong-Yu Yen, Peng-Soon Lim, Jin Ying, Hun-Jan Tao