Patents by Inventor Fong-Yuan Chang

Fong-Yuan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200411503
    Abstract: An integrated circuit includes a first region. The integrated circuit further includes a first conductive structure in the first region, wherein the first conductive structure extends in a first direction. The integrated circuit further includes a second region adjacent to the first region. The integrated circuit further includes a power structure configured to supply a voltage to the first region or the second region, wherein the power structure includes a second conductive structure overlapping a boundary between the first region and the second region, the first conductive structure and the second conductive structure are aligned in a second direction different than the first direction, and the first conductive structure and the second conductive structure are separated from each other in the first direction.
    Type: Application
    Filed: September 16, 2020
    Publication date: December 31, 2020
    Inventors: Fong-Yuan CHANG, Jyun-Hao CHANG, Sheng-Hsiung CHEN, Po-Hsiang HUANG, Lipen YUAN
  • Publication number: 20200410154
    Abstract: A method of updating a boundary space configuration of an IC layout cell includes identifying a pin in the IC layout cell as a boundary pin, determining that a boundary spacing of the boundary pin is capable of being increased, and based on the determination that the boundary spacing of the boundary pin is capable of being increased, modifying the IC layout cell by increasing the boundary spacing of the boundary pin. At least one of the identifying, determining, or modifying is executed by a processor of a computer.
    Type: Application
    Filed: September 11, 2020
    Publication date: December 31, 2020
    Inventors: Po-Hsiang HUANG, Sheng-Hsiung CHEN, Fong-Yuan CHANG
  • Patent number: 10878165
    Abstract: A method (of generating a layout diagram) includes: generating a cell (which represents a circuit) including first and second side boundaries which are substantially parallel and extend in a first direction, a first wiring pattern which is an intra-cell wiring pattern that extends in a second direction (substantially perpendicular to the first direction) and represents a conductor of a first signal which is internal to the circuit, and a second wiring pattern which extends in the first direction and represents a conductor of a second signal of the circuit; configuring the intra-cell wiring pattern so that a first end is located substantially a minimum boundary offset interior to the first side boundary; and configuring the second wiring pattern so that a portion thereof has a first end which extends exterior to the first side boundary by a protrusion length which is substantially greater than the minimum boundary offset.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-Yuan Chang, Chin-Chou Liu, Sheng-Hsiung Chen, Po-Hsiang Huang
  • Publication number: 20200402856
    Abstract: A method for forming an integrated circuit (IC) is provided. The method includes the following operations. A circuit layout including a first load region and a second load region is received. A full power network of the circuit layout is obtained. The full power network is transformed into a first power network according to the first load region. A first power simulation is performed upon the first power network. The full power network is transformed into a second power network according to the second load region. A second power simulation is performed upon the second power network. The IC is fabricated according to the circuit layout.
    Type: Application
    Filed: September 3, 2020
    Publication date: December 24, 2020
    Inventors: KA FAI CHANG, FONG-YUAN CHANG, CHIN-CHOU LIU, YI-KAN CHENG
  • Publication number: 20200395281
    Abstract: A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.
    Type: Application
    Filed: June 17, 2019
    Publication date: December 17, 2020
    Inventors: CHIN-HER CHIEN, PO-HSIANG HUANG, CHENG-HUNG YEH, TAI-YU WANG, MING-KE TSAI, YAO-HSIEN TSAI, KAI-YUN LIN, CHIN-YUAN HUANG, KAI-MING LIU, FONG-YUAN CHANG, CHIN-CHOU LIU, YI-KAN CHENG
  • Patent number: 10811316
    Abstract: A method for forming an integrated circuit (IC) is provided. The method includes the following operations. A circuit layout including a first load region and a second load region is received. A full power network of the circuit layout is obtained. The full power network is transformed into a first power network according to the first load region. A first power simulation is performed upon the first power network. The full power network is transformed into a second power network according to the second load region. A second power simulation is performed upon the second power network. The IC is fabricated according to the circuit layout.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ka Fai Chang, Fong-Yuan Chang, Chin-Chou Liu, Yi-Kan Cheng
  • Publication number: 20200327274
    Abstract: Placement methods described in this disclosure provide placement and routing rules where a system implementing the automatic placement and routing (APR) method arranges standard cell structures in a vertical direction that is perpendicular to the fins but parallel to the cell height. Layout methods described in this disclosure also improve device density and further reduce cell height by incorporating vertical power supply lines into standard cell structures. Pin connections can be used to electrically connect the power supply lines to standard cell structures, thus improving device density and performance. The APR process is also configured to rotate standard cells to optimize device layout.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung CHEN, Chung-Te Lin, Fong-Yuan Chang, Ho Che Yu, Li-Chun Tien
  • Patent number: 10804200
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Patent number: 10796060
    Abstract: A computer readable storage medium encoded with program instructions, wherein, when the program instructions is executed by at least one processor, the at least one processor performs a method. The method includes selecting a cell, determining whether a pin has an area smaller than a predetermined area, allowing a pin access of the pin to extend in a corresponding patterning track of the pin access when the pin access when the pin is determined to be having an area smaller than the predetermined threshold, and causing an integrated circuit to be fabricated according to the pin.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Fong-Yuan Chang, Li-Chun Tien, Shun-Li Chen, Ya-Chi Chou, Ting-Wei Chiang, Po-Hsiang Huang
  • Patent number: 10797041
    Abstract: An integrated circuit includes a first region and a first conductive structure in the first region, wherein the first conductive structure extends in a first direction. The integrated circuit further includes a first via coupled to the first conductive structure. The integrated circuit further includes a second region adjacent to the first region. The integrated circuit further includes a power structure configured to supply a voltage to the first or second region. The power structure includes a second conductive structure extending in the first direction and overlapping a boundary between the first region and the second region. The first conductive structure and the second conductive structure are aligned in a second direction. The first conductive structure and the second conductive structure are separated from each other in the first direction by a distance greater than a minimum spacing requirement of the first conductive structure and the second conductive structure.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fong-Yuan Chang, Jyun-Hao Chang, Sheng-Hsiung Chen, Po-Hsiang Huang, Lipen Yuan
  • Patent number: 10776557
    Abstract: A semiconductor structure includes first and second device regions. The first device region contains an entirety of a first active area of a first logic device, the second device region contains an entirety of a second active area of a second logic device, and the second device region shares a boundary with the first device region. The semiconductor structure also includes a first metal zero pin positioned partially within the first device region, partially within the second device region, and extending across the boundary, and a via contacting the first metal zero pin. A distance from the center of the via to the boundary is less than or equal to a first predetermined distance, and the via is electrically connected to one of the first logic device or the second logic device.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hsiang Huang, Sheng-Hsiung Chen, Fong-Yuan Chang
  • Patent number: 10777505
    Abstract: A method includes using a processor to placing a cell having a first conductive feature and a second conductive feature on an integrated circuit layout. A length of the first conductive feature is extended, by using the processor, to form a staggered configuration. A set of instructions for manufacturing an integrated circuit based upon the integrated circuit layout is generated, and the set of instructions is stored in a non-transitory machine readable storage medium.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fong-Yuan Chang, Sheng-Hsiung Chen, Po-Hsiang Huang, Jyun-Hao Chang, Chun-Chen Chen
  • Publication number: 20200258846
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui Yu LEE, Chin-Chou LIU, Cheng-Hung YEH, Fong-Yuan CHANG, Po-Hsiang HUANG, Yi-Kan CHENG, Ka Fai CHANG
  • Patent number: 10733352
    Abstract: Placement methods described in this disclosure provide placement and routing rules where a system implementing the automatic placement and routing (APR) method arranges standard cell structures in a vertical direction that is perpendicular to the fins but parallel to the cell height. Layout methods described in this disclosure also improve device density and further reduce cell height by incorporating vertical power supply lines into standard cell structures. Pin connections can be used to electrically connect the power supply lines to standard cell structures, thus improving device density and performance. The APR process is also configured to rotate standard cells to optimize device layout.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung Chen, Chung-Te Lin, Fong-Yuan Chang, Ho Che Yu, Li-Chun Tien
  • Patent number: 10678987
    Abstract: A method is disclosed. The method includes: obtaining a circuit design including a plurality of 2D cells of a 2D cell library; partitioning the plurality of 2D cells of the circuit design into a first group assigned to a first tier and a second group assigned to a second tier; swapping the 2D cells assigned to the first tier with corresponding 3D cells of a first type 3D cell library respectively; and swapping the 2D cells assigned to the second tier with corresponding 3D cells of a second type 3D cell library respectively; wherein at least one of the obtaining, partitioning, and swapping is performed using a processor. An associated system is also disclosed.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Sheng-Hsiung Chen, Fong-Yuan Chang
  • Publication number: 20200167518
    Abstract: A method of modifying a cell includes determining a number of pins in a maximum overlapped pin group region. The method further includes determining a number of routing tracks within a span region of the maximum overlapped pin group region. The method further includes comparing the number of pins and the number of routing tracks within the span region to determine a global tolerance of the cell. The method further includes increasing a length of at least one pin of the maximum overlapped pin group in response to the global tolerance failing to satisfy a predetermined threshold.
    Type: Application
    Filed: January 29, 2020
    Publication date: May 28, 2020
    Inventors: Sheng-Hsiung CHEN, Jyun-Hao CHANG, Ting-Wei CHIANG, Fong-Yuan CHANG, I-Lun TSENG, Po-Hsiang HUANG
  • Publication number: 20200168527
    Abstract: A device, such as a computer system, includes an interconnection device die and at least two additional device dice. The additional device dies can be system on integrated chip (SOIC) dies laying face to face (F2F) on the interconnection device die. The interconnection device die includes electrical connectors on one surface, enabling connection to and/or among the additional device dice. The interconnection device die includes at least one redistribution circuit structure, which may be an integrated fan out (InFO) structure, and at least one through-silicon via (TSV). The TSV enables connection between a signal line, power line or ground line, from an opposite surface of the interconnection device die to the redistribution circuit structure and/or electrical connectors. At least one of the additional dice can be a three-dimensional integrated circuit (3DIC) die with face to back (F2B) stacking.
    Type: Application
    Filed: September 6, 2019
    Publication date: May 28, 2020
    Applicant: Taiwan Semiconductor Manfacturing Co., Ltd.
    Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Chin-Her CHIEN, Cheny-hung YEH, Hui Yu LEE, Po-Hsiang HUANG, Yi-Kan CHENG
  • Publication number: 20200168595
    Abstract: A layout design methodology is provided for a device that includes two or more identical structures. Each device can have a first die, a second die stacked over the first die and a third die stacked over the second die. The second die can include a first through-silicon via (TSV) and a first circuit, and the third die can include a second TSV and a second circuit. The first TSV and the second TSV can be linearly coextensive. The first and second circuit can each be a logic circuit having a comparator and counter used to generate die identifiers. The counters of respective device die can be connected in series between the dice. Each die can be manufactured using the same masks but retain unique logical identifiers. A given die in a stack of dice can thereby be addressed by a single path in a same die layout.
    Type: Application
    Filed: August 2, 2019
    Publication date: May 28, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-Yuan CHANG, Chin-Chou Liu, Chin-Her Chien, Po-Hsiang Huang, Ka Fai Chang
  • Patent number: 10665550
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interposer device. The semiconductor interposer device includes a substrate and a first metallization layer formed on the substrate. A first dielectric layer is formed on the first metallization layer and a second metallization layer is formed on the substrate. A first conducting line is formed in the first metallization layer and second and third conducting lines are formed in the second metallization layer. A metal-insulator-metal (MIM) capacitor is formed in the first dielectric layer and over the first conducting line.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hui Yu Lee, Chin-Chou Liu, Cheng-Hung Yeh, Fong-Yuan Chang, Po-Hsiang Huang, Yi-Kan Cheng, Ka Fai Chang
  • Publication number: 20200152617
    Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 14, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-Yuan CHANG, Sheng-Hsiung CHEN, Ting-Wei CHIANG, Chung-Te LIN, Jung-Chan YANG, Lee-Chung LU, Po-Hsiang HUANG, Chun-Chen CHEN