Patents by Inventor Fong-Yuan Chang

Fong-Yuan Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220384414
    Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a substrate, a conductive element disposed within a first region of the substrate, and a first transistor disposed within a second region adjacent to the first region of the substrate. The conductive element is electrically connected to an electrode of the first transistor, and the conductive element penetrates the substrate and is configured to receive a supply voltage.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 1, 2022
    Inventors: CHENG-YU LIN, PO-HSIANG HUANG, POCHUN WANG, CHIH-LIANG CHEN, FONG-YUAN CHANG
  • Publication number: 20220382957
    Abstract: A system for generating a layout diagram of a wire routing arrangement in a multi-patterning context having multiple masks (the layout diagram being stored on a non-transitory computer-readable medium), at least one processor, at least one memory and computer program code (for one or more programs) of the system being configured to cause the system to execute generating the layout diagram including: placing, relative to a given one of the masks, a given cut pattern at a first candidate location over a corresponding portion of a given conductive pattern in a metallization layer; determining whether the first candidate location results in at least one of a non-circular group or a cyclic group which violates a design rule; and temporarily preventing placement of the given cut pattern in the metallization layer at the first candidate location until a correction is made which avoids violating the design rule.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Hui-Zhong ZHUANG, Meng-Kai HSU, Pin-Dai SUE, Po-Hsiang HUANG, Yi-Kan CHENG, Chi-Yu LU, Jung-Chou TSAI
  • Publication number: 20220375827
    Abstract: A device, such as a computer system, includes an interconnection device die and at least two additional device dice. The additional device dies can be system on integrated chip (SOIC) dies laying face to face (F2F) on the interconnection device die. The interconnection device die includes electrical connectors on one surface, enabling connection to and/or among the additional device dice. The interconnection device die includes at least one redistribution circuit structure, which may be an integrated fan out (InFO) structure, and at least one through-silicon via (TSV). The TSV enables connection between a signal line, power line or ground line, from an opposite surface of the interconnection device die to the redistribution circuit structure and/or electrical connectors. At least one of the additional dice can be a three-dimensional integrated circuit (3DIC) die with face to back (F2B) stacking.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 24, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-Yuan Chang, Chin-Chou Liu, Chin-Her Chien, Cheny-hung Yeh, Hui Yu Lee, Po-Hsiang Huang, Yi-Kan Cheng
  • Publication number: 20220368004
    Abstract: A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hsiang Huang, Fong-Yuan Chang, Tsui-Ping Wang, Yi-Shin Chu
  • Publication number: 20220367210
    Abstract: A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.
    Type: Application
    Filed: July 9, 2021
    Publication date: November 17, 2022
    Inventors: Ching-Yi Lin, Yu-Hao Chen, Fong-Yuan Chang, Po-Hsiang Huang, Jyh Chwen Frank Lee, Shuo-Mao Chen
  • Publication number: 20220367358
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Publication number: 20220359333
    Abstract: In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Inventors: Chen-Hua Yu, Wei Ling Chang, Chuei-Tang Wang, Fong-Yuan Chang, Chieh-Yen Chen
  • Publication number: 20220359392
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first conductive pattern on a substrate, a second conductive pattern above the first conductive pattern, and a third conductive pattern above the first conductive pattern, all extending along a first direction. The first conductive pattern is electrically connected in parallel to the second conductive pattern and the third conductive pattern.
    Type: Application
    Filed: July 29, 2021
    Publication date: November 10, 2022
    Inventors: Fei Fan DUAN, Fong-yuan CHANG, Chi-Yu LU, Po-Hsiang HUANG, Chih-Liang CHEN
  • Patent number: 11495619
    Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: November 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
  • Publication number: 20220344293
    Abstract: An interconnect structure includes a plurality of first pads arranged to form a first array and a plurality of second pads arranged to form a second array. Each of the first array has a first row, a second row and an mth row extending along a first direction and parallel to each other along a second direction. The first pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The second pads in each of the first row, the second row and the mth row are grouped into a first group, a second group and an nth group extending along the second direction. The interconnect structure further includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of nth conductive lines.
    Type: Application
    Filed: July 12, 2022
    Publication date: October 27, 2022
    Inventors: JUNG-CHOU TSAI, FONG-YUAN CHANG, PO-HSIANG HUANG, CHIN-CHOU LIU, YI-KAN CHENG
  • Publication number: 20220334167
    Abstract: A method for detecting defects in a GaN high electron mobility transistor is disclosed. The method includes steps of measuring a plurality of electrical characteristics of a GaN high electron mobility transistor, measuring the plurality of electrical characteristics after performing a deterioration test on the GaN high electron mobility transistor, irradiating the GaN high electron mobility transistor in turns with a plurality of light sources with different wavelengths and measuring the plurality of electrical characteristics after each irradiation of the GaN high electron mobility transistor by each of the plurality of light sources, and comparing changes of the plurality of electrical characteristics measured in the above steps to determine the defect location of the GaN high electron mobility transistor.
    Type: Application
    Filed: June 10, 2021
    Publication date: October 20, 2022
    Inventors: Ting-Chang CHANG, Hao-Xuan ZHENG, Yu-Shan LIN, Fu-Yuan JIN, Fong-Min CIOU, Mao-Chou TAI, Yun-Hsuan LIN, Wei-Chen HUANG, Wen-Chung CHEN
  • Publication number: 20220335199
    Abstract: A semiconductor device including a cell region which includes components representing a circuit arranged such that a rectangular virtual perimeter is drawable around substantially all of the components and includes first and second virtual side boundaries, the components including: a first conductor which is an intra-cell conductor of a first signal that is internal to the circuit, a first end of the intra-cell conductor being substantially a minimum virtual boundary offset inside the first virtual side boundary; and a second conductor of a second signal of the circuit; a portion of the second conductor having a first end which extends outside the first virtual side boundary by a protrusion length substantially greater than the minimum virtual boundary offset; and a second end of the second conductor being receded inside the second virtual side boundary by a first gap substantially greater than the minimum virtual boundary offset.
    Type: Application
    Filed: July 6, 2022
    Publication date: October 20, 2022
    Inventors: Fong-Yuan CHANG, Chin-Chou LIU, Sheng-Hsiung CHEN, Po-Hsiang HUANG
  • Publication number: 20220336356
    Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Fong-Yuan Chang, Noor Mohamed Ettuveettil, Po-Hsiang Huang, Sen-Bor Jan, Ming-Fa Chen, Chin-Chou Liu, Yi-Kan Cheng
  • Publication number: 20220328409
    Abstract: In some embodiments, a low-resistance path between an active cell and a power supply layer in an integrated circuit device includes at least one layer of a plurality of conductive lines commonly connected to at least one conductive line through a plurality of respective conductive pillars, the at least one conductive line being in the power supply layer or intervening the active cell and the power supply layer. In some embodiments, the integrated circuit device includes a conductive layer that includes the plurality of conductive lines and additional conductive portions, where the plurality of conductive lines are isolated from the additional conductive portions.
    Type: Application
    Filed: November 30, 2021
    Publication date: October 13, 2022
    Inventors: Ho-Che Yu, Fong-yuan Chang, Po-Hsiang Huang, Ching-Yi Lin, Chen-Yi Chang
  • Publication number: 20220320018
    Abstract: An interposer includes one or more capacitors to store charge to provide signals to an integrated circuit electrically connected to the interposer. First connectors to each capacitor are interspersed with second connectors to the capacitors and are spaced apart from adjacent second connectors. The one or more capacitors and the resistances associated with the conductive paths between each capacitor and a connector or another capacitor can be modeled.
    Type: Application
    Filed: June 17, 2022
    Publication date: October 6, 2022
    Inventors: Fong-yuan CHANG, Cheng-Hung YEH, Hsiang-Ho CHANG, Po-Hsiang HUANG, Chin-Her CHIEN, Sheng-Hsiung CHEN, Aftab Alam KHAN, Keh-Jeng CHANG, Chin-Chou LIU, Yi-Kan CHENG
  • Publication number: 20220310480
    Abstract: Packaged semiconductor devices including high-thermal conductivity molding compounds and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first redistribution structure; a first die over and electrically coupled to the first redistribution structure; a first through via over and electrically coupled to the first redistribution structure; an insulation layer extending along the first redistribution structure, the first die, and the first through via; and an encapsulant over the insulation layer, the encapsulant surrounding portions of the first through via and the first die, the encapsulant including conductive fillers at a concentration ranging from 70% to about 95% by volume.
    Type: Application
    Filed: August 2, 2021
    Publication date: September 29, 2022
    Inventors: Xinyu Bao, Lee-Chung Lu, Jyh Chwen Frank Lee, Fong-yuan Chang, Sam Vaziri, Po-Hsiang Huang
  • Patent number: 11437319
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Patent number: 11437708
    Abstract: A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Hsiang Huang, Fong-Yuan Chang, Tsui-Ping Wang, Yi-Shin Chu
  • Publication number: 20220262418
    Abstract: A memory device includes a plurality of circuit layers, a plurality of first conductive through via structures and a plurality of bitlines. The circuit layers are disposed one above another, and each circuit layer includes one or more memory cell arrays. The first conductive through via structures penetrates though the circuit layers. Each of the bitlines includes a plurality of bitline segments disposed on the circuit layers respectively. The bitline segments are electrically connected through one of the first conductive through via structures. Each bitline segment is coupled to a plurality of memory cells of a memory cell array of a circuit layer where the bitline segment is disposed.
    Type: Application
    Filed: April 29, 2022
    Publication date: August 18, 2022
    Inventors: SHIH-LIEN LINUS LU, FONG-YUAN CHANG, YI-CHUN SHIH
  • Patent number: 11410929
    Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: August 9, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Noor Mohamed Ettuveettil, Po-Hsiang Huang, Sen-Bor Jan, Ming-Fa Chen, Chin-Chou Liu, Yi-Kan Cheng