Abstract: A method of fabricating a semiconductor device with Shallow Trench Isolation (STI) includes performing the following steps in the following sequence: providing a substrate comprising first and second gate regions separated by a trench formed in the substrate, wherein the trench is filled with an STI material. The method further includes depositing a sacrificial polysilicon layer covering the STI material; growing a thick oxide layer on the first and second gate regions; removing the thick oxide layer from the first gate region while leaving the thick oxide layer in the second gate region.

Abstract: A method of fabricating a semiconductor device with Shallow Trench Isolation (STI) includes performing the following steps in the following sequence: providing a substrate comprising first and second gate regions separated by a trench formed in the substrate, wherein the trench is filled with an STI material. The method further includes depositing a sacrificial polysilicon layer covering the STI material; growing a thick oxide layer on the first and second gate regions; removing the thick oxide layer from the first gate region while leaving the thick oxide layer in the second gate region.

Abstract: A MOS device assembly having at least two transistors, each transistor having a gate region. The dimensions of the gate region of the first transistor are different from the dimensions of the gate region of the second transistor. The transconductance of the MOS device assembly is substantially uniform when the gate regions of the first and second transistors are biased using the same voltage.

Abstract: A MOS device assembly having at least two transistors, each transistor having a gate region. The dimensions of the gate region of the first transistor are different from the dimensions of the gate region of the second transistor. The transconductance of the MOS device assembly is substantially uniform when the gate regions of the first and second transistors are biased using the same voltage.