Abstract: Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer.

Abstract: Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer.

Abstract: Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer.

Abstract: Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes providing a substrate prepared with a memory cell region. A first gate structure is formed on the memory cell region. An isolation layer is formed on the substrate and over the first gate structure. A second gate structure is formed adjacent to and separated from the first gate structure by the isolation layer. The first and second gate structures are processed to form at least one split gate structure with first and second adjacent gates. Asymmetrical source and drain regions are provided adjacent to first and second sides of the split gate structure.

Abstract: Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer.

Abstract: Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes providing a substrate prepared with a memory cell region. A first gate structure is formed on the memory cell region. An isolation layer is formed on the substrate and over the first gate structure. A second gate structure is formed adjacent to and separated from the first gate structure by the isolation layer. The first and second gate structures are processed to form at least one split gate structure with first and second adjacent gates. Asymmetrical source and drain regions are provided adjacent to first and second sides of the split gate structure.

Abstract: Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes providing a substrate prepared with a memory cell region. A first gate structure is formed on the memory cell region. An isolation layer is formed on the substrate and over the first gate structure. A second gate structure is formed adjacent to and separated from the first gate structure by the isolation layer. The first and second gate structures are processed to form at least one split gate structure with first and second adjacent gates. Asymmetrical source and drain regions are provided adjacent to first and second sides of the split gate structure.

Abstract: Integrated circuits with multi-level memory cells and methods for producing the same are provided. A method for producing an integrated circuit with a multi-level memory cell includes forming a gate insulator overlying a substrate. A select gate is formed overlying the gate insulator such that one multi-level memory cell includes one select gate. A thin film storage layer with nanocrystals is formed overlying the select gate and the substrate, and a left and right control gate are formed on opposite sides of the select gate such that the thin film storage layer is between the substrate and each of the control gates. A left implant and a right implant are formed in the substrate such that the select gate, the left control gate, and the right control gate are positioned between the left and right implants.

Abstract: Integrated circuits with multi-level memory cells and methods for producing the same are provided. A method for producing an integrated circuit with a multi-level memory cell includes forming a gate insulator overlying a substrate. A select gate is formed overlying the gate insulator such that one multi-level memory cell includes one select gate. A thin film storage layer with nanocrystals is formed overlying the select gate and the substrate, and a left and right control gate are formed on opposite sides of the select gate such that the thin film storage layer is between the substrate and each of the control gates. A left implant and a right implant are formed in the substrate such that the select gate, the left control gate, and the right control gate are positioned between the left and right implants.

Abstract: Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes providing a substrate prepared with a memory cell region. A first gate structure is formed on the memory cell region. An isolation layer is formed on the substrate and over the first gate structure. A second gate structure is formed adjacent to and separated from the first gate structure by the isolation layer. The first and second gate structures are processed to form at least one split gate structure with first and second adjacent gates. Asymmetrical source and drain regions are provided adjacent to first and second sides of the split gate structure.

Abstract: Methods are provided for manufacturing a thin film storage memory cell. The method includes forming a long select gate on a substrate, and forming thin film storage crystals overlying the long select gate and the adjacent substrate. A left and right control gate are formed on opposite sides of the long select gate, and a long select gate center portion is removed to form a left select gate and a right select gate with a gap therebetween. A drain is formed in the substrate underlying the gap, and a left and right source are formed in the substrate aligned with the left and right control gate.