Patents by Inventor Foong Yue Ho

Foong Yue Ho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8680686
    Abstract: A system and method for a thin multi chip stack package with film on wire and copper wire. The package comprises a substrate and a first die overlying the substrate. Copper wires electrically connect the first die to the substrate. A film overlies the first die and a portion of the copper wires. In addition, the film adheres a second die to the first die. The film also electrically insulates the copper wires from the second die.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: March 25, 2014
    Assignee: Spansion LLC
    Inventors: Lai Nguk Chin, Foong Yue Ho, Wong Kwet Nam, Thor Lee Lee, Sally Foong, Kevin Guan
  • Patent number: 8357563
    Abstract: A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: January 22, 2013
    Assignee: Spansion LLC
    Inventors: Lai Nguk Chin, Foong Yue Ho, Wong Kwet Nam, Koo Eng Luon, Sally Foong, Kevin Guan
  • Publication number: 20120038059
    Abstract: A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.
    Type: Application
    Filed: August 10, 2010
    Publication date: February 16, 2012
    Inventors: Lai Nguk CHIN, Foong Yue HO, Wong Kwet NAM, Koo Eng LUON, Sally FOONG, Kevin GUAN
  • Publication number: 20110316158
    Abstract: A system and method for a thin multi chip stack package with film on wire and copper wire. The package comprises a substrate and a first die overlying the substrate. Copper wires electrically connect the first die to the substrate. A film overlies the first die and a portion of the copper wires. In addition, the film adheres a second die to the first die. The film also electrically insulates the copper wires from the second die.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 29, 2011
    Inventors: Lai Nguk CHIN, Foong Yue HO, Wong Kwet NAM, Thor Lee LEE, Sally FOONG, Kevin GUAN
  • Patent number: 7932131
    Abstract: A method and structure for reducing the size of semiconductor package is disclosed. In one example embodiment, a method for stacking dies of a semiconductor package includes forming a set of insulated bonding wires between respective bonding pads of a first semiconductor integrated circuit die and a conductive layer electrically detached from the respective bonding pads, applying an adhesive material on a top surface of the first semiconductor integrated circuit die, and securing a second semiconductor integrated circuit die one the top surface of the first semiconductor integrated circuit die with the adhesive material.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: April 26, 2011
    Assignee: Spansion LLC
    Inventors: Sally Foong, Kevin Guan, Changhak Lee, Lai Nguk Chin, Royce Yeoh Kao Tziat, Foong Yue Ho
  • Publication number: 20090115033
    Abstract: A method and structure for reducing the size of semiconductor package is disclosed. In one example embodiment, a method for stacking dies of a semiconductor package includes forming a set of insulated bonding wires between respective bonding pads of a first semiconductor integrated circuit die and a conductive layer electrically detached from the respective bonding pads, applying an adhesive material on a top surface of the first semiconductor integrated circuit die, and securing a second semiconductor integrated circuit die one the top surface of the first semiconductor integrated circuit die with the adhesive material.
    Type: Application
    Filed: November 5, 2007
    Publication date: May 7, 2009
    Inventors: Sally Foong, Kevin Guan, Changhak Lee, Lai Nguk Chin, Royce Yeoh Kao Tziat, Foong Yue Ho