Abstract: A method and system for interactive home monitoring includes detecting a visitor arriving at a premises of a multimedia content distribution network (MCDN) client by an intercom unit installed at the premises. The intercom unit may be coupled to the MCDN client, which may be configured to wirelessly communicate with a user of the MCDN client. A captured image of the visitor may be used to determine if an identity of the visitor is known or unknown. Based on the identity, a communication channel between the visitor and the user may be established at the intercom unit. The intercom unit may further be configured to provide further information to the visitor based on the visitor identity.

Abstract: A method for doping terminals of a field-effect transistor (FET), the FET including a drain region, a source region, and a surround gate surrounding a channel region, the method including depositing a dopant-containing layer, such that the surround gate prevents the dopant-containing layer from contacting the channel region of the FET, the dopant-containing layer including a dopant. The dopant then diffuses the dopant from the dopant-containing layer into at least one of the drain region and source region of the FET.

Abstract: An apparatus for abatement of gases is provided. The apparatus includes a toroidal plasma chamber having a plurality of inlets and an outlet, and at least one chamber wall. One or more magnetic cores are disposed relative to the toroidal plasma chamber. The plasma chamber confines a toroidal plasma. A second gas inlet is positioned on the toroidal plasma chamber between a first gas inlet and the gas outlet at a distance d from the gas outlet, such that a toroidal plasma channel volume between the first gas inlet and the second gas inlet in the is substantially filled by the inert gas, the distance d based on a desired residence time of the gas to be abated.

Abstract: A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory elements formed utilizing two etches through all epitaxially grown layers. Each of these etches can be split to two separate processes specific to CMOS transistor etch and to memory element etch. The memory array device includes a plurality of gate conductors configured along a first axis, in parallel. Each FET of the memory cells adjacent to two gate conductors. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis.

Abstract: Computing interface systems and methods are disclosed. Some implementations include a first accelerometer attached to a first fastening article that is capable of holding the first accelerometer in place on a portion of a thumb of a user. Some implementations may also include a second accelerometer attached to a second fastening article that is capable of holding the second accelerometer in place on a portion of a wrist of a user. Some implementations may additionally or alternatively include magnetometers and/or gyroscopes attached to the first and second fastening articles. Some implementations may also include a processing device configured to receive measurements from the accelerometers, magnetometers, and/or gyroscopes and identify, based on the measurements, symbols associated with motions of a user's hand and/or the orientation of the hand. Some implementations may allow a user to control a cursor in a three dimensional virtual space and interact with objects in that space.

Abstract: A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory elements formed utilizing two etches through all epitaxially grown layers. Each of these etches can be split to two separate processes specific to CMOS transistor etch and to memory element etch. The memory array device includes a plurality of gate conductors configured along a first axis, in parallel. Each FET of the memory cells adjacent to two gate conductors. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis.

Abstract: A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory array device includes a plurality of gate conductors configured a first axis, in parallel. Each gate conductor laterally surrounds a plurality of FETs of the memory cells along the first axis. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis. Embodiments of the memory array preserve alignment of crystal lattices beginning from the bottom layers in the FET up to the top active layers in memory element, thus preserving crystal lattice alignment between transistor and memory element.

Abstract: A transmitter is carried proximate to an inground tool for sensing a plurality of operational parameters relating to the inground tool. The transmitter customizes a data signal to characterize one or more of the operational parameters for transmission from the inground tool based on the operational status of the inground tool. A receiver receives the data signal and recovers the operational parameters. Advanced data protocols are described. Pitch averaging and enhancement of dynamic pitch range for accelerometer readings are described based on monitoring mechanical shock and vibration of the inground tool.

Abstract: A stent crimping tool insert comprises a core body configured for insertion into and removal from within a crimping chamber of a stent crimping tool. The core body has a core surface configured to withstand a compressive force without a reduction in diameter of the core surface.

Abstract: A dilation device comprises an elongate shaft, an inflatable balloon, and a resilient tube. The inflatable balloon is disposed along the shaft. The resilient tube is also disposed along the shaft and is positioned to encompass at least part of the inflatable balloon. The resilient tube is configured to impose an inwardly directed resilient bias on at least a portion of the exterior of the inflatable balloon. At least part of the resilient tube is secured to one or both of the elongate shaft or the inflatable balloon.

Abstract: Error correction operations in memory devices are disclosed. In at least one embodiment, an internal controller of a memory device periodically performs internal error correction operations on stored user data and corrects user data in the memory device independently from instructions from an external memory access device.

Abstract: According to one general aspect, a method may include executing, by a processor of a computing device, at least a portion of an application that includes a plurality of tabs, each tab associated with a respective document that is configured to be rendered for display by the application. The method may also include determining a particular tab of the plurality of tabs that is recording an audio and/or visual signal derived from an environment of the computing device. The method may further include providing a graphical indication, associated with the particular tab, that indicates to a user of the computing device that the particular tab is recording the audio and/or visual signal.

Abstract: A computing system may include a base portion to receive one or more first batteries, and a tablet portion having one or more electronic components and the tablet portion to receive one or more second batteries. The tablet portion may be configured to be coupled to and detached from the base portion. The computing system may also include circuitry to control a supply of voltage to one or more electronic components of the tablet portion from one or more first batteries at the base portion and from one or more second batteries at the tablet portion.

Abstract: A wear leveling technique is employed in a memory device so that the cycling history of a memory block is represented by the cycling history of a representative memory cell or a small number of representative memory cells. A control logic block tracks the cycling history of the one or more representative memory cells. A table tabulating the predicted shift in an optimal value for a reference variable for a sensing circuit as a function of cycling history is provided within the memory device. Prior to sensing a memory cell, the control logic block checks the total number of cycling in the one or more representative memory cells and adjusts the value for the reference variable in the sensing circuit, thereby providing an optimal value for the reference variable in the sensing circuit for each sensing cycle of the memory device.

Abstract: A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory array device includes a plurality of gate conductors configured a first axis, in parallel. Each gate conductor laterally surrounds a plurality of FETs of the memory cells along the first axis. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis. Embodiments of the memory array preserve alignment of crystal lattices beginning from the bottom layers in the FET up to the top active layers in memory element, thus preserving crystal lattice alignment between transistor and memory element.

Abstract: A wear leveling technique is employed in a memory device so that the cycling history of a memory block is represented by the cycling history of a representative memory cell or a small number of representative memory cells. A control logic block tracks the cycling history of the one or more representative memory cells. A table tabulating the predicted shift in an optimal value for a reference variable for a sensing circuit as a function of cycling history is provided within the memory device. Prior to sensing a memory cell, the control logic block checks the total number of cycling in the one or more representative memory cells and adjusts the value for the reference variable in the sensing circuit, thereby providing an optimal value for the reference variable in the sensing circuit for each sensing cycle of the memory device.

Abstract: The present disclosure provides compounds of Formula I: or a pharmaceutically acceptable salt thereof, wherein R5, R6 and Z are as described herein. The disclosure also provides pharmaceutical compositions thereof; and methods for inhibiting DHFR activity; and methods for treating cell proliferative diseases, autoimmune disease, inflammatory disease or bacterial, fungal or parasitic infection by administering a compound of Formula I.

Abstract: An air gun firing operating system that uses compressed air to eject bullets by a purely mechanical device, and enables single firing or high-speed continuous firing. During the firing operation, the system uses a sliding shuttle tube that is able to slide back and forth in a linear displacement on a central axis between a bullet chamber and a cylinder. The sliding shuttle tube uses differential pressure variation in a pressure buffer chamber to achieve a stroke state that can be continuously changed, thereby achieving high-speed back and forth motion and continuous firing of bullets. The relevant driving position of a trigger device is provided with a sliding retainer, which is able to effect transient retaining of the sliding shuttle tube, thereby restricting the system for single firing, or discontinuing the retention to enable the system to be in a continuous firing operation state.

Abstract: A system and method recover water from an ambient airstream. Dehumidification of the airstream is also achieved by removal of the water. A device of the system includes a chamber having a group of trays that hold respective amounts of liquid desiccant in each tray. A foam media absorbs the desiccant to increase an exposed surface of the desiccant to the airstream. Fans and valves are used to control airflow through the device. A charge cycle circulates air through the device to remove water vapor from the airstream. A subsequent extraction cycle removes water collected in the liquid desiccant by a condenser communicating with the chamber. An integral heat exchanger adds heat to the chamber during the extraction cycle. A controller is used to integrate and manage all system functions and input variables to achieve a high efficiency of operational energy use for water collection.

Abstract: An example embodiment is a circuit for determining a binary value of a memory cell. The circuit includes shunt capacitors having different capacitances to selectively couple with the memory cell, and a controller configured to iteratively charge the shunt capacitors to a first voltage until a selected shunt capacitor causes the first voltage to decay through the memory cell to a first reference voltage within a predetermined time range, determine a binary value of the most significant bits of the memory cell based on the selected shunt capacitor, charge the selected shunt capacitor to a second voltage after determining the binary value of the most significant bits of the memory cell, and determine a binary value of the least significant bits of the memory cell based on a decay of the second voltage at the selected shunt capacitor through the memory cell.