Patents by Inventor Forest Dillinger

Forest Dillinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEM AND METHOD FOR CONSTANT CHARACTERISTIC IMPEDANCE IN A FLEXIBLE TRACE INTERCONNECT ARRAY
    Publication number: 20110298567
    Abstract: A system for matching impedance in a flexible trace interconnect array. The array comprising a flexible dielectric film, a plurality of trace conductors disposed along a longitudinal axis of the dielectric film, and a shield disposed along a section of the array, wherein at least one parameter of at least one of an unshielded section and of the shielded section is selected such that impedance of the unshielded section and impedance of the shielded section are substantially the same.
    Type: Application
    Filed: August 19, 2011
    Publication date: December 8, 2011
    Applicant: Oracle America, Inc., formerly known as Sun Microsystems, Inc.
    Inventors: Kevin Dale McKinstry, Otto Richard Buhler, Jeffrey Glenn Villiard, Forest Dillinger
  • Power distribution for high-speed integrated circuits
    Patent number: 7919804
    Abstract: An improved technique for power distribution for use by high speed integrated circuit devices. A mixture of high dielectric constant, Er and low Er materials are used in a dielectric layer sandwiched between the voltage and ground planes of a printed circuit board that is used to fixture one or more integrated circuit devices. The low Er material is used in an area contained by the location of the integrated circuit device and its corresponding decoupling capacitors located nearby. High Er material is used in areas between the regions of low Er material. The low Er material improves that speed at which current from an adjoining decoupling capacitor can propagate to a power pin of the integrated circuit device. The high Er material mitigates cross-coupling of noise between the low Er regions.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: April 5, 2011
    Assignee: Oracle America, Inc.
    Inventors: Kevin Horn, Forest Dillinger, Otto Richard Buhler, Karl Sauter
  • POWER DISTRIBUTION FOR HIGH-SPEED INTEGRATED CIRCUITS
    Publication number: 20070102806
    Abstract: An improved technique for power distribution for use by high speed integrated circuit devices. A mixture of high dielectric constant, Er and low Er materials are used in a dielectric layer sandwiched between the voltage and ground planes of a printed circuit board that is used to fixture one or more integrated circuit devices. The low Er material is used in an area contained by the location of the integrated circuit device and its corresponding decoupling capacitors located nearby. High Er material is used in areas between the regions of low Er material. The low Er material improves that speed at which current from an adjoining decoupling capacitor can propagate to a power pin of the integrated circuit device. The high Er material mitigates cross-coupling of noise between the low Er regions.
    Type: Application
    Filed: December 1, 2006
    Publication date: May 10, 2007
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Kevin Horn, Forest Dillinger, Otto Buhler, Karl Sauter