Abstract: A memory controller reads data from a memory bank of synchronous RAM during a small and variable data valid window, by compensating for delays in receiving the data caused by memory loading, chip and card manufacturing process variations, and the like. The memory controller includes a system clock driver to supply the memory bank with a clock reference signal. A sampling clock provides an assortment of sampling clock signals duplicative of the system clock signal, with various delays. A command driver initiates Read operations in the memory bank by relaying Read command signals to the memory bank. In response to the level of memory loading, such as the number of memory modules present in the memory bank, a clock selector directs a selected one of the sampling clock signals to a delay module, which replicates any delay the system clock driver may have.

Abstract: A systematic method for detecting which head in a multiple head storage device contains errors and may be misaligned, and correcting for misalignment so that the data can be recovered. The apparatus includes a data buffer for storing a block of interleaved data read from the multiple head storage device, status bits, error detection circuitry for determining from the interleaved data, which if any of the heads is misaligned and for setting the status bits, data recovery control logic responsive to the status bits for sending control signals to the multiple head storage device for causing the misaligned head to move its position by small increments and to read data until the status bits indicate that the misaligned head has become aligned, and circuitry responsive to the status bits for writing data from the newly realigned head over the data which was read when that head was misaligned.