Abstract: Disclosed is a bridge system and method for prefetching data to return to a read request from an agent. The bridge system includes at least one memory device including a counter indicating a number of prefetch operations to perform to prefetch all the requested data, a first buffer capable of storing prefetch requests, and a second buffer capable of storing read data. Control logic implemented in the bridge system includes means for queuing at least one prefetch operation in the first buffer while the counter is greater than zero. The control logic then executes a queued prefetch operation, subsequently receives the prefetched data, and stores the prefetched data in the second buffer. The stored prefetched data is returned to the requesting agent.

Abstract: Disclosed is a system for processing read/write transactions from a plurality of agents over a bus. The bridge includes at least one request buffer for each agent in communication with the bridge. The request buffer for an agent buffers transactions originating from that agent. The bridge further includes a return buffer for each agent in communication with the bridge. The return buffer for an agent buffers return data in connection with a transaction. Address translation circuitry is in communication with the bus and request and return buffers. The address translation circuitry locates a request buffer to queue the transaction, such that a transaction is stored in the request buffer corresponding to the agent that originated the transaction. Further, the address translation circuitry stores read return data for a read transaction in the return buffer corresponding to the agent originating the transaction.

Abstract: Disclosed is a bridge system for processing read and write transactions over a bus in which in a preferred embodiment continuous read data obtained from a target device in a number of separate read operations over a secondary bus may be gathered by the bridge and assembled into a larger block of data before forwarding the data over the primary bus to the requesting agent. As a consequence, the transmission of optimal, address boundary-aligned bursts of read data over the primary bus may be increased and conversely, the transmission of fractionated, nonaligned read data over the primary bus may be reduced. Because each agent is assigned particular buffers, read data may be gathered concurrently in the assigned bridge buffers without assertion of a read request by one agent causing the flushing of the data being gathered for a different agent.

Abstract: Aspects for caching storage data include partitioning a storage cache to include a compressed data partition and an uncompressed data partition, and adjusting a size of the compressed data partition and the uncompressed data partition for chosen performance characteristics. A data caching system aspect in a data processing system having a host system in communication with a storage system includes at least one storage device and at least one partially compressed cache. The at least one partially compressed cache further includes an uncompressed partition and a compressed partition, where the compressed partition stores at least a victim data unit from the uncompressed partition.

Abstract: Disclosed is a bridge system for processing read transactions over a bus in which in a preferred embodiment prefetched data stored in a buffer is not discarded if the address of the requested read does not match the beginning address of the prefetched data. Instead, the bridge system skips to the next address of the prefetched data stored in the buffer and compares that address to the address of the read request to determine if a match exists. If the requested read address does match the next prefetched data address, the prefetched data starting at that next address is read out and forwarded to the requesting agent. Alternatively, if there is not a match, the bridge skips again to the next address and continues checking for a match until either the prefetched data is exhausted or another predetermined limit has been reached. In this manner, many unnecessary data reads of data already prefetched in the buffer may be avoided.

Abstract: Aspects for caching storage data include partitioning a storage cache to include a compressed data partition and an uncompressed data partition, and adjusting a size of the compressed data partition and the uncompressed data partition for chosen performance characteristics. A data caching system aspect in a data processing system having a host system in communication with a storage system includes at least one storage device and at least one partially compressed cache. The at least one partially compressed cache further includes an uncompressed partition and a compressed partition, where the compressed partition stores at least a victim data unit from the uncompressed partition.

Abstract: Disclosed is a system for communication among a device, a first processor, and a second processor. One of a first data path and second data path is configured. The first data path comprises a bus, such as a local PCI bus, a first remote bridge, and a first local bridge. The bridges may be comprised of PCI to PCI bridges. After configuring the first data path, the device communicates to the first processor by communicating data through the bus to the first remote bridge. The first remote bridge transmits the data to the first local bridge and the first local bridge transmits the data to the first processor. The second data path comprises the bus, a second remote bridge, and a second local bridge. After configuring the second data path, the device communicates to the second processor by communicating data through the bus to the second remote bridge. The second remote bridge transmits the data to the second local bridge and the second local bridge transmits the data to the second processor.

Abstract: A data storage system and method for securely storing data includes (a) a host CPU; (b) a non-volatile storage (NVS) memory for storing data; (c) a processor, the processor being coupled to the host CPU and the NVS memory and monitoring availability of space in the NVS memory and in a non-volatile buffer (NV-Buffer); and (d) the NV-Buffer, the NV-Buffer being coupled to the host CPU, the NVS memory, and the processor, upon receiving a request to write data into the NVS memory, the host CPU storing data to be transferred to the NVS memory into the NV-Buffer, and upon receiving a confirmation message that data of a write operation to the NV-Buffer is committed, the NV-Buffer transferring the data to the NVS memory. The NVS memory includes a fast dump space for storing data transferred from the NV-Buffer when a main power is down and for restoring back data from the NVS memory to the NV-Buffer when the power is up.