Abstract: Data communication between a processing unit and external means may take place via a plurality of data streams. Means check the mutual consistency of said streams and report and correct abnormalities. This self-synchronization is achieved by inserting separators into the data streams to separate the data, and by means of a freezing mechanism for freezing the internal operation of the processing unit.

Abstract: The program memory comprises a first segment (MP1) containing a succession of program words including first base words (MMA) each having a size less than the sum of the respective sizes of the control words destined for the execution units (UXi), and second base words (MMB) fewer in number than that of the first base words. Facilities sequentially extract the various program words from the first segment of the program memory. A storage facility (RG) is connected to the output of the program memory. Facilities (MXM) update the content of the storage facility at least on the basis of each extracted second base word, and computational facilities (MEB) sequentially compute certain at least of the various groups of control words, on the basis of the combining according to at least one predetermined logic relation, of the content of the storage facility and of an extracted first base word, so as to minimize the memory size of the said program code.

Abstract: A first and a second input ports, the sum of whose inputs is greater than an integer n, receive pairs of first words of k bits and of second words of n-k bits, each set of n bits representing an address item (ADI) for a point (PO) of a two-dimensional space of points (IM) associated with data coded on 2.sup.d bits, the respective bits of the first and second words representing two coordinates (X, Y) of the point in the said space. A configuration input receives a value of k (k1, k2, k3), chosen to be positive or zero and less than or equal to n, and representative of a geometrical configuration chosen for the two-dimensional?s!?pace! space (IM).

Abstract: The component essentially includes three subtracter operators (ST1-ST3) connected between two multiplexers (MUX1, MUX2), associated with a shifter (DEC) for shifting the dividend and a concatenator means (MCT) for delivering the successive partial dividends from the contents of an output flip-flop (B3) and from the successive shifted words (S). The final-result word is stored in a shift register (RG). The component may be applied to image processing.