Abstract: A turbine includes a stator and a movable rotor, rotating around an axis, in relation to the stator. The rotor comprises at least one disc, the radially outer periphery of which comprises cavities. The rotor further includes blades, each having a blade root axially engaged in a cavity of the disc so as to radially hold the blade on the disc. At least one of the blade roots has an axially flaring shape, with the corresponding cavity having a matching shape so as to axially lock the blade root in the cavity in a first axially oriented direction. Locking means lock the blade root in the cavity in a second axially oriented direction, opposite the first direction.

Abstract: An apparatus has register rename circuitry to map architectural register specifiers specified by instructions to physical register specifiers identifying physical registers. A restoration table identifies at least one restoration mapping between an architectural register specifier and a previously mapped physical register specifier. Register reserving circuitry indicates one or more reserved register specifiers. In response to detecting that a speculative instruction corresponding to a restoration mapping has been committed when that instruction or an older instruction still could potentially read a register, the register reserving circuitry indicates the physical register specifier of that restoration mapping as reserved.

Abstract: An apparatus comprising: a set of registers; and mapping circuitry to perform a mapping operation to map each of a set of register specifiers to a respective register from among the set of registers in dependence on a mapping function. The mapping function is dependent on a key value. In addition, the mapping for at least two register specifiers from among the set of register specifiers is dependent on the same key value.

Abstract: An apparatus and method are provided for controlling use of a register cache. The apparatus has execution circuitry for executing instructions to process data values, and a register file comprising a plurality of registers in which to store the data values for access by the execution circuitry. A register cache is also provided that has a plurality of entries and is arranged to cache a subset of the data values for access by the execution circuitry. Each entry is arranged to cache a data value and an indication of the register associated with that cached data value. Prefetch circuitry then performs prefetch operations to prefetch data values from the register file into the register cache. Timing indication storage is used to store, for each data value to be generated as a result of instructions being executed within the execution circuitry, a register identifier for that data value, and timing information indicating when that data value will be generated by the execution circuitry.

Abstract: A leading-edge shield (32) for a turbomachine blade (16) includes a pressure-side wing (34) and a suction-side wing (36). Each of the wings (34, 36) extends along a height (H) from a bottom edge (50) to a top edge (51) and along a length, from the leading edge to a respective rear edge, and are connected together over the leading edge. At least one of the wings from among the suction-side wing (36) and the pressure-side wing (34) presents a segment (S1), adjacent to the top edge (51) and extending over at least 10% of the height (H), wherein the rear edge (42) slopes towards the top edge (51).

Abstract: An apparatus and method are provided for controlling use of a register cache. The apparatus has decode circuitry for decoding instructions retrieved from memory, execution circuitry to execute the decoded instructions in order to perform operations on data values, and a register file having a plurality of registers for storing the data values to be operated on by the execution circuitry. Further, a register cache is provided that comprises a plurality of entries, and is arranged to cache a subset of the data values. Each entry is arranged to cache a data value and an indication of the register associated with that cached data value. Prefetch circuitry is then used to prefetch data values from the register file into the register cache. Further, operand analysis circuitry derives source operand information for an instruction fetched from memory, at least prior to the decode circuitry completing decoding of that instruction.

Abstract: An apparatus has processing circuitry to perform data processing in one of two or more operating states associated with different levels of privilege. At least one operating state holding element holds a state indication indicating a current operating state of the processing circuitry. In response to a transition of a reset signal from a first value to a second value for triggering a reset of the processing circuitry, the at least one operating state holding element resets the state indication to indicate a default operating state other than a most privileged operating state of the two or more operating states.

Abstract: An apparatus has a number of data holding elements for holding data values which are reset to a reset value in response to a transition of a signal at a reset signal input of the data holding element from a first value to a second value. A reset tree is provided to distribute a reset signal received at root node of the reset tree to the reset signal inputs of the data holding elements. At least one reset attack detection element is provided, with its reset signal input coupled to a given node of the reset tree, to assert an error signal when its reset signal input transitions from the first value to a second value. Reset error clearing circuitry triggers clearing of the error signal, when the reset signal at the root node of the reset tree transitions from the second value to the first value.

Abstract: The invention relates to the field of turbomachine blades, and more specifically to a leading-edge shield (32) for a turbomachine blade (16), said leading-edge shield (32) including a pressure-side wing (34) and a suction-side wing (36). Each pressure-side wing (34) and suction-side wing (36) extends heightwise from a bottom edge (50) to a top edge (51) and lengthwise from the leading edge (18) to a rear edge (40, 42), and they are connected together via the leading edge (18), and wherein the rear edge (42) of the suction-side wing (36) presents at least one shaped segment (S1, S2) that is shaped in such a manner that the length of the suction-side wing (36) within this segment is shorter than the length (l2, l3, l21, l22, l31, l32) of the suction-side wing (36) at each end of this segment (S1, S2).

Abstract: The invention provides a blade (16) comprising a blade body (30) made of organic matrix composite material reinforced by fibers and a leading edge shield (32) made of a material that withstands point impacts better than the composite material of the blade body. The leading edge shield (32) is assembled on the blade body (30) and the blade (16) includes bonding reinforcement (46) adhesively bonded on the leading edge shield (32) and on the blade body (16). The invention also provides a turbojet including a fan including such blades, and also a method of fabricating such a blade.

Abstract: A blade including a blade body made of organic matrix composite material and a leading edge shield made of a material that withstands point impacts better than the composite material of the blade body. The blade includes a blade tip. The leading edge shield is assembled on the blade body and includes a pressure-side fin and a suction-side fin. The pressure-side fin includes a pressure-side tab and the suction-side fin includes a suction-side tab, the pressure-side tab and the suction-side tab are folded one on the other and being secured to each other so as to form a partial covering of the blade tip. A turbojet includes a fan including such blades, and also a method of fabricating such a blade.

Abstract: A data processing system 2 includes multiple out-of-order issue queues 8, 10. A master serialization instruction MSI received by a first issue queue 8 is detected by slave generation circuitry 24 which generates a slave serialization instruction SSI added to a second issue queue 10. The master serialization instruction MSI manages serialization relative to the instructions within the first issue queue 8. The slave serialization instruction SSI manages serialization relative to the instructions within the second issue queue 10. The master serialization instruction MSI and the slave serialization instruction SSI are removed when both have met their serialization conditions and are respectively the oldest instructions within their issue queues.

Abstract: The invention relates to a method (100) for manufacturing a turbomachine fan comprising a plurality of blades mounted on a disc extending along a longitudinal axis, said method comprising the following steps of: —measuring (102) at least one structural parameter of each of the blades in the cold state, and, for each of the blades, estimating (103) at least one structural parameter in operation relating to a blade from the structural parameter(s) measured on said blade in the cold state, —determining (104) an optimal sequence of the blades around the disc from the structural parameters estimated in operation for each of the blades, and —mounting (105) the blades on the disc in the optimal sequence thus determined.

Abstract: The invention relates to a blade made of composite material, provided with a reinforcement (17) made of a stronger material with regard to a leading edge (5) likely to be struck by solid objects, which comprises, under the aerodynamic portion of the blade, extensions (18, 19) attached to the blade root. According to the invention, the extensions (18, 19) are dissymmetric, the extension (18) located on the suction side being generally further back from the leading edge (5) than the extension (19) on the pressure side.

Abstract: A method for aligning a set of solar modules of a solar tracker includes a means of connection and of transmission of a solar-tracking movement between two adjacent solar modules of the set of solar modules. The method includes an iterative loop that includes, for each on-going iteration, steps of: disconnecting adjacent solar modules of an aligned subset of solar modules derived from a previous iteration; defining which one of the previously disconnected adjacent solar modules will be the reference solar module for the on-going iteration; orienting the aligned subset of solar modules in such a way that the solar modules of the aligned subset of solar modules are aligned with the reference solar module; connecting the aligned subset of solar modules with the reference solar module for the on-going iteration so as to define an aligned subset of solar modules for the next iteration.

Abstract: An apparatus has register rename circuitry to map architectural register specifiers specified by instructions to physical register specifiers identifying physical registers. A restoration table identifies at least one restoration mapping between an architectural register specifier and a previously mapped physical register specifier. Register reserving circuitry indicates one or more reserved register specifiers. In response to detecting that a speculative instruction corresponding to a restoration mapping has been committed when that instruction or an older instruction still could potentially read a register, the register reserving circuitry indicates the physical register specifier of that restoration mapping as reserved.

Abstract: A data processing system 2 includes multiple out-of-order issue queues 8, 10. A master serialisation instruction MSI received by a first issue queue 8 is detected by slave generation circuitry 24 which generates a slave serialisation instruction SSI added to a second issue queue 10. The master serialisation instruction MSI manages serialisation relative to the instructions within the first issue queue 8. The slave serialisation instruction SSI manages serialisation relative to the instructions within the second issue queue 10. The master serialisation instruction MSI and the slave serialisation instruction SSI are removed when both have met their serialisation conditions and are respectively the oldest instructions within their issue queues.

Abstract: A data processing apparatus comprises register rename circuitry for mapping architectural register specifiers specified by instructions to physical registers to be accessed in response to the instructions. Available register control circuitry controls which physical registers are available for mapping to an architectural register specifier by the register rename circuitry. For at least one group of two or more physical registers, the available register control circuitry controls availability of the registers based on a group tracking indication indicative of whether there is at least one pending access to any of the physical registers in the group.

Abstract: An apparatus and method includes execution circuitry including a wide operand execution unit configured to allow up to N bits of operand data to be processed during execution of a single instruction. Decoder circuitry decodes and generates, for each instruction, at least one control data block identifying an operation to be performed by the execution circuitry and at least two re-combineable control data blocks for the instruction. Issue queue control circuitry then allocates a slot in the issue queue for each of the at least two data blocks and up to M bits of associated operand data, and marks those allocated slots to identify that they contain re-combineable control data blocks. The issue queue control circuitry issues the combined block to said wide operand execution unit along with the operand data contained in each of the allocated slots for said at least two control data blocks.

Abstract: Register renaming circuitry for a processing apparatus configured to process a stream of instructions from an instruction set specifying registers from an architectural set of registers. The apparatus including a physical set of registers configured to store data values being processed by the processing apparatus. Register renaming circuitry is configured to receive a stream of operations from an instruction decoder and to map registers that are to be written to by the stream of operations to physical registers within the physical set of registers that are currently available. The register renaming circuitry comprises register release circuitry configured to release the physical registers that have been mapped to the registers when a first set of conditions have been met, and to release the physical registers that have been mapped to the additional registers when a second set of conditions have been met.