Patents by Inventor Frédéric Lanois
Frédéric Lanois has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220393022Abstract: A trench in a semiconductor substrate is lined with a first insulation layer. A hard mask layer deposited on the first insulation layer is used to control performance of an etch that selectively removes a first portion of the first insulating layer from an upper trench portion while leaving a second portion of first insulating layer in a lower trench portion. After removing the hard mask layer, an upper portion of the trench is lined with a second insulation layer. An opening in the trench that includes a lower open portion delimited by the second portion of first insulating layer in the lower trench portion and an upper open portion delimited by the second insulation layer at the upper trench portion, is then filled by a single deposition of polysilicon material forming a unitary gate/field plate conductor of a field effect rectifier diode.Type: ApplicationFiled: April 27, 2022Publication date: December 8, 2022Applicants: STMicroelectronics PTE LTD, STMicroelectronics (Tours) SASInventors: Shin Phay LEE, Voon Cheng NGWAN, Frederic LANOIS, Fadhillawati TAHIR, Ditto ADNAN
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Publication number: 20220360072Abstract: The present disclosure relates to a transient voltage suppression device comprising a single crystal semiconductor substrate doped with a first conductivity type comprising first and second opposing surfaces, a semiconductor region doped with a second conductivity type opposite to the first conductivity type extending into the substrate from the first surface, a first electrically conductive electrode on the first side contacting the semiconductor region and a second electrically conductive electrode on the second side contacting the substrate, a first interface between the substrate and the semiconductor region forming the junction of a TVS diode and a second interface between the first electrically conductive electrode and the semiconductor region or between the substrate and the second electrically conductive electrode forming the junction of a Schottky diode.Type: ApplicationFiled: April 29, 2022Publication date: November 10, 2022Inventors: Jean-Michel Simonnet, David Jouve, Frédéric Lanois
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Publication number: 20220123155Abstract: The present disclosure relates to a structure comprising, in a trench of a substrate, a first conductive region separated from the substrate by a first distance shorter than approximately 10 nm; and a second conductive region extending deeper than the first region.Type: ApplicationFiled: December 30, 2021Publication date: April 21, 2022Applicant: STMICROELECTRONICS (TOURS) SASInventor: Frederic LANOIS
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Patent number: 11239376Abstract: The present disclosure relates to a structure comprising, in a trench of a substrate, a first conductive region separated from the substrate by a first distance shorter than approximately 10 nm; and a second conductive region extending deeper than the first region.Type: GrantFiled: September 26, 2019Date of Patent: February 1, 2022Assignee: STMicroelectronics (Tours) SASInventor: Frederic Lanois
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Patent number: 10903311Abstract: A diode includes upper and lower electrodes and first and second N-type doped semiconductor substrate portions connected to the lower electrode. A first vertical transistor and a second transistor are formed in the first portion and series-connected between the electrodes. The gate of the first transistor is N-type doped and coupled to the upper electrode. The second transistor has a P channel and has a P-type doped gate. First and second doped areas of the second conductivity type are located in the second portion and are separated by a substrate portion topped with another N-type doped gate. The first doped area is coupled to the gate of the second transistor. The second doped area and the other gate are coupled to the upper electrode.Type: GrantFiled: November 20, 2018Date of Patent: January 26, 2021Assignee: STMICROELECTRONICS (TOURS) SASInventors: Frédéric Lanois, Alexei Ankoudinov, Vladimir Rodov
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Patent number: 10784787Abstract: A circuit includes a first field-effect transistor and a second field-effect transistor. The first field-effect transistor includes a first diode with drain, source, gate and first additional electrodes. The second field-effect transistor includes a second diode with drain, source, gate and second additional electrodes. A first switch selectively connects the gate and drain electrodes of the first field-effect transistor. A second switch selectively connects the gate and drain electrodes of the second field-effect transistor. A control circuit controls the first and second switches. The first additional electrode is coupled to the gate electrode of the second field-effect transistor, and the second additional electrode is coupled to the gate electrode of the first field-effect transistor.Type: GrantFiled: October 28, 2014Date of Patent: September 22, 2020Assignee: STMICROELECTRONICS (TOURS) SASInventors: Bertrand Rivet, Greca Jean Charles, Frederic Lanois
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Publication number: 20200105946Abstract: The present disclosure relates to a structure comprising, in a trench of a substrate, a first conductive region separated from the substrate by a first distance shorter than approximately 10 nm; and a second conductive region extending deeper than the first region.Type: ApplicationFiled: September 26, 2019Publication date: April 2, 2020Inventor: Frederic Lanois
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Publication number: 20190088735Abstract: A diode includes upper and lower electrodes and first and second N-type doped semiconductor substrate portions connected to the lower electrode. A first vertical transistor and a second transistor are formed in the first portion and series-connected between the electrodes. The gate of the first transistor is N-type doped and coupled to the upper electrode. The second transistor has a P channel and has a P-type doped gate. First and second doped areas of the second conductivity type are located in the second portion and are separated by a substrate portion topped with another N-type doped gate. The first doped area is coupled to the gate of the second transistor. The second doped area and the other gate are coupled to the upper electrode.Type: ApplicationFiled: November 20, 2018Publication date: March 21, 2019Inventors: Frédéric Lanois, Alexei Ankoudinov, Vladimir Rodov
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Patent number: 10177218Abstract: A diode includes upper and lower electrodes and first and second N-type doped semiconductor substrate portions connected to the lower electrode. A first vertical transistor and a second transistor are formed in the first portion and series-connected between the electrodes. The gate of the first transistor is N-type doped and coupled to the upper electrode. The second transistor has a P channel and has a P-type doped gate. First and second doped areas of the second conductivity type are located in the second portion and are separated by a substrate portion topped with another N-type doped gate. The first doped area is coupled to the gate of the second transistor. The second doped area and the other gate are coupled to the upper electrode.Type: GrantFiled: November 30, 2016Date of Patent: January 8, 2019Assignee: STIMICROELECTRONICS (TOURS) SASInventors: Frédéric Lanois, Alexei Ankoudinov, Vladimir Rodov
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Publication number: 20170301752Abstract: A diode includes upper and lower electrodes and first and second N-type doped semiconductor substrate portions connected to the lower electrode. A first vertical transistor and a second transistor are formed in the first portion and series-connected between the electrodes. The gate of the first transistor is N-type doped and coupled to the upper electrode. The second transistor has a P channel and has a P-type doped gate. First and second doped areas of the second conductivity type are located in the second portion and are separated by a substrate portion topped with another N-type doped gate. The first doped area is coupled to the gate of the second transistor. The second doped area and the other gate are coupled to the upper electrode.Type: ApplicationFiled: November 30, 2016Publication date: October 19, 2017Inventors: Frédéric Lanois, Alexei Ankoudinov, Vladimir Rodov
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Publication number: 20150117063Abstract: A circuit includes a first field-effect transistor and a second field-effect transistor. The first field-effect transistor includes a first diode with drain, source, gate and first additional electrodes. The second field-effect transistor includes a second diode with drain, source, gate and second additional electrodes. A first switch selectively connects the gate and drain electrodes of the first field-effect transistor. A second switch selectively connects the gate and drain electrodes of the second field-effect transistor. A control circuit controls the first and second switches. The first additional electrode is coupled to the gate electrode of the second field-effect transistor, and the second additional electrode is coupled to the gate electrode of the first field-effect transistor.Type: ApplicationFiled: October 28, 2014Publication date: April 30, 2015Applicant: STMICROELECTRONICS (TOURS) SASInventors: Bertrand Rivet, Greca Jean Charles, Frederic Lanois
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Patent number: 7683454Abstract: A MOS power component in which the active regions extend perpendicularly to the surface of a semiconductor chip substantially across the entire thickness thereof. A MOS power transistor according to the present invention alternately includes a source region of a first conductivity type, an intermediary region, and a drain region of the first conductivity type, each of these regions extending across the entire thickness of the substrate, the source and drain regions being contacted by conductive fingers or plates substantially crossing the substrate, insulated and spaced apart conductive fingers crossing from top to bottom the intermediary region, the horizontal distance between the insulated fingers being such that the intermediary region can be inverted when an appropriate voltage is applied to these insulated fingers.Type: GrantFiled: January 22, 2004Date of Patent: March 23, 2010Assignee: STMicroelectronics S.A.Inventors: Jean-Baptiste Quoirin, Frédéric Lanois
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Patent number: 7622752Abstract: A Schottky diode with a vertical barrier extending perpendicularly to the surface of a semiconductor chip having a vertical central metal conductor in contact on the one hand with the substrate of the semiconductor chip with an interposed interface forming a Schottky barrier, and on the other hand with radially-extending conductive fingers.Type: GrantFiled: December 23, 2005Date of Patent: November 24, 2009Assignees: STMicroelectronics S.A., STMicroelectronics MarocInventors: Frédéric Lanois, Sylvain Nizou
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Patent number: 7411248Abstract: A vertical unipolar component formed in a semiconductor substrate, comprising vertical fingers made of a conductive material surrounded with silicon oxide, portions of the substrate being present between the fingers and the assembly being coated with a conductive layer. The component periphery includes a succession of fingers arranged in concentric trenches, separated from one another by silicon oxide only, the upper surface of the fingers of at least the innermost rank being in contact with said conductive layer.Type: GrantFiled: December 8, 2005Date of Patent: August 12, 2008Assignee: STMicroelectronics S.A.Inventor: Frédéric Lanois
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Patent number: 7220644Abstract: The invention relates to a vertical-type single-pole component, comprising regions with a first type of conductivity which are embedded in a thick layer with a second type of conductivity. Said regions are distributed over at least one same horizontal level and are independent of each other. The regions also underlie an insulating material.Type: GrantFiled: April 27, 2005Date of Patent: May 22, 2007Assignee: STMicroelectronics S.A.Inventor: Frédéric Lanois
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Publication number: 20060205196Abstract: A vertical unipolar component formed in a semiconductor substrate. An upper portion of the substrate includes insulated trenches filled with a vertical multiple-layer of at least two conductive elements separated by an insulating layer, the multiple-layer depth being at most equal to the thickness of the upper portion.Type: ApplicationFiled: April 28, 2006Publication date: September 14, 2006Applicant: STMicroelectronics S.A.Inventor: Frederic Lanois
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Patent number: 7101739Abstract: A method for manufacturing a vertical Schottky diode with a guard ring on a lightly-doped N-type silicon carbide layer, including forming a P-type epitaxial layer on the N-type layer; implanting N-type dopants in areas of the P-type epitaxial layer to neutralize in these areas, across the entire thickness of the epitaxial layer, the P-type dopants to form N-type regions, of dopant concentration lower than that of the epitaxial layer, and delimiting a P-type guard ring; forming on the external periphery of the component an insulating layer partially covering the guard ring; and forming a Schottky contact with the N-type region internal to the guard ring.Type: GrantFiled: November 20, 2002Date of Patent: September 5, 2006Assignee: STMicroelectronics S.A.Inventor: Frédéric Lanois
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Publication number: 20060157745Abstract: A TMBS-type Schottky diode including main electrodes on active areas on the upper surface side and a main electrode on the lower surface side, including on the upper surface side conductive fingers penetrating between the active areas and biased, directly or indirectly, like the active areas. The fingers includes closer portions on their upper portion side than on their bottom side. The fingers preferably are polysilicon fingers insulated by an insulating layer such as silicon oxide.Type: ApplicationFiled: January 17, 2006Publication date: July 20, 2006Applicant: STMicroelectronics S.A.Inventor: Frederic Lanois
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Patent number: 7078783Abstract: A vertical unipolar component formed in a semiconductor substrate. An upper portion of the substrate includes insulated trenches filled with a vertical multiple-layer of at least two conductive elements separated by an insulating layer, the multiple-layer depth being at most equal to the thickness of the upper portion.Type: GrantFiled: January 29, 2004Date of Patent: July 18, 2006Assignee: STMicroelectronics S.A.Inventor: Frédéric Lanois
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Publication number: 20060138450Abstract: A Schottky diode with a vertical barrier extending perpendicularly to the surface of a semiconductor chip having a vertical central metal conductor in contact on the one hand with the substrate of the semiconductor chip with an interposed interface forming a Schottky barrier, and on the other hand with radially-extending conductive fingers.Type: ApplicationFiled: December 23, 2005Publication date: June 29, 2006Applicant: STMicroelectronics S.A.Inventors: Frederic Lanois, Sylvain Nizou