Abstract: The invention relates to a test device for an analog circuit to be mounted on a mixed circuit including said analog circuit and a synchronous digital circuit. The test device includes a disturbance emulator connected to a first supply source (UrefD) capable of disturbing a second supply source (UrefA) of the analog circuit, the first and second supply sources being optionally merged, the emulator being adapted for receiving data representative of the evolution, during a given duration, of the average (?I) and the typical deviation (?I) of a first inrush current (I) that would be applied to the first supply source by the digital circuit, and being adapted for applying to the first supply source during successive intervals, each successive interval having said duration, a second inrush current (Irep) equal to the sum of the average and of the product of the typical deviation and of a pseudo-random signal varying according to a Gaussian law.

Abstract: The invention relates to a test device (20) for an analog circuit (12) to be mounted on a mixed circuit (10) including said analog circuit and a synchronous digital circuit. The test device includes a disturbance emulator (22) connected to a first supply source (UrefD) capable of disturbing a second supply source (UrefA) of the analog circuit, the first and second supply sources being optionally merged, the emulator being adapted for receiving data representative of the evolution, during a given duration, of the average (?I) and the typical deviation (?I) of a first inrush current (I) that would be applied to the first supply source by the digital circuit, and being adapted for applying to the first supply source during successive intervals, each successive interval having said duration, a second inrush current (Irep) equal to the sum of the average and of the product of the typical deviation and of a pseudo-random signal varying according to a Gaussian law.

Abstract: A method for simulating an electric circuit comprising components and receiving external stimuli, wherein the determination at a given time of the voltages at the circuit nodes comprises several iterations, each consisting of defining a probable voltage for each node, of calculating the currents of each component based on the component model, then of repeating until the mesh equation is verified, and wherein for the first time, a current of a component is calculated based either on the full accurate model, or on the simplified linear model, or on the compound model which is a fitting, according to the interval between the voltages at the component's terminals between the initial time and the first time, and the simplified, full or compound model is used respectively if the interval is smaller than a first threshold, greater than a second threshold or between the first and second thresholds.

Abstract: A method for simulating an electric circuit comprising components and receiving external stimuli, wherein the determination at a given time of the voltages at the circuit nodes comprises several iterations, each consisting of defining a probable voltage for each node, of calculating the currents of each component based on the component model, then of repeating until the mesh equation is verified, and wherein for the first time, a current of a component is calculated based either on the full accurate model, or on the simplified linear model, or on the compound model which is a fitting, according to the interval between the voltages at the component's terminals between the initial time and the first time, and the simplified, full or compound model is used respectively if the interval is smaller than a first threshold, greater than a second threshold or between the first and second thresholds.

Abstract: A ROM including a set of memory points arranged in rows and columns, in which each memory point, formed of a single controllable switch, memorizes an N-bit information, with N>=2. Each column includes 2N conductive lines; each of the two main terminals of each memory point is connected to one of said conductive lines, each information value being associated with a specific assembly of 2N connections from among the set of 22N possible connections; and each of N read means is provided to apply a precharge voltage to a chosen group of 2N−1 first lines, connect the 2N−1 other lines to a reference voltage, select a memory point, read the voltages from the first lines, combine the obtained results to provide an indication of the value of one of the bits of the information contained in the selected memory point.

Abstract: A ROM including a set of memory points arranged in rows and columns, in which each memory point, formed of a single controllable switch, memorizes an N-bit information, with N>2. Each column includes 2N conductive lines; each of the two main terminals of each memory point is connected to one of said conductive lines, each information value being associated with a specific assembly of 2N connections from among the set of the 22N possible connections; and each of N read means is provided to apply a precharge voltage to a chosen group of 2N−1 first lines, connecting the 2N−1 other lines to a reference voltage, select a memory point, read the voltages from the first lines, combine the obtained results to provide an indication of the value of one of the bits of the information contained in the selected memory point.

Abstract: A method of fractional division of a frequency of a digital signal from N replicas of said digital signal shifted in phase with respect to one another by 2&pgr;/N. This method consists of selecting a first replica to generate the rising edge and a second replica to generate the falling edge, the first and second replicas of a period of the resulting signal being different from the first and second replicas used in the next period.

Abstract: A method of simulation of an electronic circuit including a plurality of components having variable characteristics, including an initialization step consisting of giving each variable characteristic a value from a set of predetermined values deterministically linked to a single initialization value likely to be memorized.

Abstract: A method of fractional division of a frequency of a digital signal from N replicas of said digital signal shifted in phase with respect to one another by 2&pgr;/N. This method consists of selecting a first replica to generate the rising edge and a second replica to generate the falling edge, the first and second replicas of a period of the resulting signal being different from the first and second replicas used in the next period.