Abstract: An oscillator circuit produces first and second oscillating logic signals that are of a same frequency and are non-overlapping in a first logic state. This oscillator includes a flip-flop circuit to produce third and fourth oscillating logic signals of opposite polarities, this flip-flop circuit being driven by first and second driving logic signals. First and second logic gates receive the third and fourth logic signals and produce the first and second logic signals, the logic state transitions in the first and second logic signals being produced as a function of the logic state transitions of the third and fourth logic signals. The first and second logic gates are organized so as to introduce a delay into the transitions from a second logic state to the first logic state, in the first and second logic signals, with respect to transitions in the third and fourth logic signals.

Abstract: An integrated circuit comprises a memory zone, a test mode and at least one binary type of lock, said lock when it is in a first state permitting the operation of the integrated circuit in the test mode and when it is in a second state prohibiting the operation of the integrated circuit in test mode, wherein the integrated circuit comprises a dysfunction circuit that works when the lock is in the first state, said dysfunction circuit preventing the memory from working normally. The use of a dysfunction circuit makes it possible to reveal components whose test locks have not been activated as being defective.

Abstract: A method and device for encoding and transmitting a clock signal, a supply voltage and bidirectional digital data from a master circuit to a slave circuit, including the steps of: holding a first conductor at a first voltage with respect to a second conductor; periodically raising the first conductor to a second voltage with respect to the second conductor, a fixed period after a previous raising to the second voltage; holding the first conductor at the second voltage for one of a number of predetermined periods, then returning the first conductor to the first voltage, the voltage of the first conductor not falling below the first voltage; controlling the predetermined periods to each have one of a number of fixed durations, each duration having a logical significance.

Abstract: Disclosed is a high voltage generator circuit of the charge pump type. The rate of operation of this pump is set by a sequence of piloting signals produced out of a clock signal. This clock signal is itself produced by an oscillator. A frequency servo-link is set up between the clock signal produced by the oscillator and the running of the sequence in order to produce a clock signal with a frequency that is equal to the maximum permissible frequency for low supply voltages while at the same time limiting this frequency from a given supply voltage threshold onwards.

Abstract: A digital ramp generator including a controlled sampling circuit receiving an input voltage, an adding circuit for adding the said input voltage to an actual output voltage to provide a new voltage which is greater than the said input voltage, and a voltage follower circuit receiving the new voltage and providing a new output voltage corresponding to the new voltage which is greater than the said actual output voltage.