Abstract: A device for generating a high voltage includes a charge pump device that outputs a high voltage, an oscillator that supplies at least one clock signal to the charge pump device, and a regulation device. The regulation device generates a control signal to selectively stop the charge pump device based on the level of the high voltage output by the charge pump device. Additionally, the oscillator includes a shaping circuit for shaping the clock signal into a saw-tooth waveform. In a preferred embodiment, the oscillator supplies at least two clock signals to the charge pump device, and each of the clock signals has a saw-tooth waveform. A method for generating a high voltage in an integrated circuit is also provided. According to the method, at least one clock signal is generated, and the clock signal is shaped into a saw-tooth waveform. The shaped clock signal is used to generate a high voltage, and the generation of the high voltage is selectively stopped based on the level of the high voltage.

Abstract: A fuse for an integrated circuit is constituted by a shallow NP junction, covered with a metal contact, the semiconductor region being not excessively doped. For the blowing of the fuse, the junction is forward biased with a current sufficient to enable a diffusion of metal up to the junction. This short-circuits the junction. The detection is done also by the forward biasing of the junction, but with a low current or a low voltage. The detection can also be done with reverse biasing.

Abstract: In a device for the protection of integrated circuits against electrostatic discharges, the protection structure comprises a thyristor with an N+ region connected to the ground, a P- substrate, a deep N- well forming a gate region, and a P+ region connected to an external connection pad to be protected. The gate region is connected by a low-value resistor (with a maximum value of a few ohms) to the pad. This resistor increases the current for which the thyristor gets triggered and eliminates certain risks of the destruction of the circuit.

Abstract: A current reference device in integrated circuit form with a reference resistor includes a first MOS transistor and a second MOS transistor having the same type of conductivity, the first transistor having its gate and its drain connected together to a first terminal of the reference resistor, the second transistor having its gate and its drain connected together to a second terminal of the reference resistor, the first transistor having a threshold voltage greater than that of the second transistor, these two transistors being biased in saturated mode, the source of each of these transistors being biased at the same potential as the substrate or the well in which the transistor is made.

Abstract: In order to reduce the number of lines of a standard bus while, at the same time, preserving the compatibility of the communications protocol, the system uses a modified bus. The modification consists in eliminating two power supply lines and in creating a line assigned to a functional signal that is complementary to one of the functional signals of the system. The supply potentials are regenerated from the functional signal and the complementary signal. The disclosed system can be applied notably to systems using I2C buses such as systems using chip-card readers.

Abstract: The disclosure relates to integrated circuits and methods in which it is desired to implement a partition of a memory between a protected zone and a non-protected zone, the dimensions of the protected zone being defined by a customer of the memory. A disclosed method avoids the use of special instructions to define these dimensions. The method includes writing sensitive information elements by starting at an address ADP, and ending at an address ADFM dictated by the circuit. The writing in the address ADFM automatically triggers a sequence for storing, in a non-volatile register RV, the first written address, and a sequence for the activation of a system for the protection of the zone between the addresses ADP and ADFM.

Abstract: A circuit including a network of capacitors and switching transistors having two modes of functioning. The first mode isolates all the capacitors and simultaneously charges them to the level of the supply voltage. The second mode connects all these capacitors in series between the supply voltage Vdd and an output node of the network in order to instantaneously increase the voltage level of this output node to a voltage level that is greater than the supply voltage Vdd. The capacitors are all connected in series by transistors that are placed between them and controlled by a signal that has a peak voltage that is greater than the voltage to be switched to the output node of the network.

Abstract: In order to make it possible to ascertain that the programming cycles in an EEPROM type memory have been carried out efficiently, supplementary test cells are provided. A data writing operation is carried out in three successive cycles that consist in the programming of a test cell with a first logic value, a second cycle for the programming of the data elements and a third cycle for the programming of the test cell with a logic value that is complementary to the first one. The state of the test cell enables the detection of power interruptions during programming.

Abstract: The present invention describes a resistance reference circuit that includes a reference resistor that is substantially independent of temperature variations to which the resistance reference circuit is subjected. Also provided is a resistor network that may be dependant upon the temperature variations, and a current source circuit that provides first and second currents to the reference resistor and the resistor network. A circuit that is responsive to voltages developed across the reference resistor and the resistor network modifies the resistance value of the resistor network such that its resistance value is maintained the same as that of the reference resistor.

Abstract: A fuse for an integrated circuit is constituted by a shallow NP junction, covered with a metal contact, the semiconductor region being not excessively doped. For the blowing of the fuse, the junction is forward biased with a current sufficient to enable a diffusion of metal up to the junction. This short-circuits the junction. The detection is done also by the forward biasing of the junction, but with a low current or a low voltage. The detection can also be done with reverse biasing.

Abstract: A method and apparatus for reading a memory, such that the address decoding is started when the address bits have not yet all been received. All the information elements corresponding to the partially decoded address are extracted and, when the last address bits have been received, the information element corresponding to the complete address is selected. The maximum permissible time for extracting an information element is thus increased internally, while this period of time external to the memory remains the same for a given frequency.

Abstract: A resistor-capacitor-transistor type of integrated circuit comprises mainly a non-self-aligned N diffusion bar 1 covered with a polysilicon plate, and a drain type N diffusion, self-aligned by the polysilicon plate. The resulting structure is a distributed resistor-capacitor-transistor quadripole whose main characteristics are that it is very compact and that the time taken by the capacitor to get discharged through the transistor is independent of the dimensions of the structure.

Abstract: In a method for the testing of integrated circuits on wafers, the testing is facilitated by setting apart a test circuit zone on the wafer. The test circuit zone comprises contact pads to which it is possible to apply the tips of a tester, and also comprises a demultiplexer to transmit test stimuli to one out of N buses at the output of the demultiplexer. The output buses of the demultiplexer extend between the rows of chips on the wafer. Column selection conductors extend between the columns of chips. The demultiplexer and a decoder, both controlled directly by the tester, enable the selection of one chip at a time for testing. The testing tips are not shifted from one chip to the next one. The wafer is then sliced into individual chips.

Abstract: To prompt a repairing operation as and when defective cells appear in an integrated circuit memory, there is provided an auxiliary memory related to a programmable comparator. Whenever the cells of the memory are to be read, the auxiliary memory is read and its content is compared with the address selected in the memory array. The result of this comparison produces, in real time, the addressing signals of a redundant cell and signals for the neutralization of the initially encountered cell. This system can be used more particularly in the field of EEPROM type memories.

Abstract: In a device for the protection of integrated circuits against electrostatic discharges, the protection structure comprises a thyristor with an N+ region connected to the ground, a P- substrate, a deep N- well forming a gate region, and a P+ region connected to an external connection pad to be protected. The gate region is connected by a low-value resistor (with a maximum value of a few ohms) to the pad. This resistor increases the current for which the thyristor gets triggered and eliminates certain risks of the destruction of the circuit.