Patents by Inventor Francois Leverd
Francois Leverd has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230005735Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.Type: ApplicationFiled: September 8, 2022Publication date: January 5, 2023Applicant: STMicroelectronics (Crolles 2) SASInventors: Delia RISTOIU, Pierre BAR, Francois LEVERD
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Patent number: 11469095Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.Type: GrantFiled: December 10, 2019Date of Patent: October 11, 2022Assignee: STMicroelectronics (Crolles 2) SASInventors: Delia Ristoiu, Pierre Bar, Francois Leverd
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Publication number: 20220028726Abstract: A method for forming a capacitive isolation trench in a semiconductor substrate includes digging a trench from a main surface of the substrate, the trench including an upper portion gradually widening from a neck in the direction of a lower portion of the trench. A coating of a first electrically isolating material is formed on the walls of the trench. A first semiconductor material is deposited on the coating, with the deposition being interrupted so as to leave a free space between the walls of the trench, the free space having an opening at the neck. A second electrically isolating material is deposited in the trench, with the deposition resulting in the formation of a plug closing the opening to form a closed cavity. The plug is etched so as to open the cavity, and a second semiconductor material or a metal is deposited so as to fill the cavity.Type: ApplicationFiled: July 15, 2021Publication date: January 27, 2022Applicant: STMicroelectronics (Crolles 2) SASInventors: Denis MONNIER, Francois LEVERD
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Patent number: 10770306Abstract: A cavity is etched in a stack of layers which includes a first layer made of a first material and a second layer made of a second material. To etch the cavity, a first etch mask having a first opening is formed over the stack of layer. The stack of layers is then etched through the first opening to a depth located in the second layer. A second mask having a second opening, the dimensions of which are smaller, in top view, than the first opening, is formed over the stack of layer. The second opening is located, in top view, opposite the area etched through the first opening. The second layer is then etched through the second opening to reach the first layer. The etch method used is configured to etch the second material selectively over the first material.Type: GrantFiled: January 4, 2019Date of Patent: September 8, 2020Assignee: STMicroelectronics (Crolles 2) SASInventors: Pierre Bar, Francois Leverd, Delia Ristoiu
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Publication number: 20200211835Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.Type: ApplicationFiled: December 10, 2019Publication date: July 2, 2020Applicant: STMicroelectronics (Crolles 2) SASInventors: Delia RISTOIU, Pierre BAR, Francois LEVERD
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Publication number: 20190214270Abstract: A cavity is etched in a stack of layers which includes a first layer made of a first material and a second layer made of a second material. To etch the cavity, a first etch mask having a first opening is formed over the stack of layer. The stack of layers is then etched through the first opening to a depth located in the second layer. A second mask having a second opening, the dimensions of which are smaller, in top view, than the first opening, is formed over the stack of layer. The second opening is located, in top view, opposite the area etched through the first opening. The second layer is then etched through the second opening to reach the first layer. The etch method used is configured to etch the second material selectively over the first material.Type: ApplicationFiled: January 4, 2019Publication date: July 11, 2019Applicant: STMicroelectronics (Crolles 2) SASInventors: Pierre BAR, Francois LEVERD, Delia RISTOIU
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Patent number: 8847344Abstract: An integrated imaging device includes a silicon layer provided over a dielectric multilayer. The dielectric multilayer includes a top silicon-dioxide layer, an intermediate silicon-nitride layer and a bottom silicon-dioxide layer. Imaging circuitry is formed at a frontside of the silicon layer. An isolating structure surrounds the imaging circuitry and extends from the frontside through the silicon layer and top silicon-dioxide layer into and terminating within the intermediate silicon-nitride layer. A filter for the imaging circuitry is mounted to a backside of the bottom silicon-dioxide layer. The isolating structure is formed by a trench filled with a dielectric material.Type: GrantFiled: May 30, 2012Date of Patent: September 30, 2014Assignee: STMicroelectronics (Croles 2) SASInventors: Francois Roy, Francois Leverd, Jens Prima
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Patent number: 8796148Abstract: A method for producing a deep trench in a substrate includes a series of elementary etch cycles each etching a portion of the trench. Each elementary cycle includes deposition of a passivation layer on the sidewalls and the bottom of the trench portion etched during previous cycles; followed by pulsed plasma anisotropic ion etching of the trench portion etched during previous cycles, the etching; being implemented in an atmosphere comprising a passivating species; and including a first etch sequence followed by a second etch sequence of less power than the power of the first etch sequence. The first etch sequence etches the passivation layer deposited in the bottom of the portion so as to access the substrate and etches the free substrate at the bottom of the portion while leaving a passivation layer on sidewalls of the portion.Type: GrantFiled: August 30, 2012Date of Patent: August 5, 2014Assignee: STMicroelectronics (Crolles 2) SASInventors: François Leverd, Laurent Favennec, Arnaud Tournier
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Patent number: 8436440Abstract: A method for manufacturing a back-side illuminated image sensor, including the steps of: forming, inside and on top of an SOI-type silicon layer, components for trapping and transferring photogenerated carriers and isolation regions; forming a stack of interconnection levels on the silicon layer and attaching, on the interconnect stack, a semiconductor handle; removing the semiconductor support; forming, in the insulating layer and the silicon layer, trenches reaching the isolation regions; depositing a doped amorphous silicon layer, more heavily doped than the silicon layer, at least on the walls and the bottom of the trenches and having the amorphous silicon layer crystallize; and filling the trenches with a reflective material.Type: GrantFiled: November 9, 2010Date of Patent: May 7, 2013Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.Inventors: Michel Marty, François Leverd
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Publication number: 20130052829Abstract: A method for producing a deep trench in a substrate includes a series of elementary etch cycles each etching a portion of the trench. Each elementary cycle includes deposition of a passivation layer on the sidewalls and the bottom of the trench portion etched during previous cycles; followed by pulsed plasma anisotropic ion etching of the trench portion etched during previous cycles, the etching; being implemented in an atmosphere comprising a passivating species; and including a first etch sequence followed by a second etch sequence of less power than the power of the first etch sequence. The first etch sequence etches the passivation layer deposited in the bottom of the portion so as to access the substrate and etches the free substrate at the bottom of the portion while leaving a passivation layer on sidewalls of the portion.Type: ApplicationFiled: August 30, 2012Publication date: February 28, 2013Applicant: STMicroelectronics (Crolles 2) SASInventors: Francois Leverd, Laurent Favennec, Arnaud Tournier
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Publication number: 20120306035Abstract: An integrated imaging device includes a silicon layer provided over a dielectric multilayer. The dielectric multilayer includes a top silicon-dioxide layer, an intermediate silicon-nitride layer and a bottom silicon-dioxide layer. Imaging circuitry is formed at a frontside of the silicon layer. An isolating structure surrounds the imaging circuitry and extends from the frontside through the silicon layer and top silicon-dioxide layer into and terminating within the intermediate silicon-nitride layer. A filter for the imaging circuitry is mounted to a backside of the bottom silicon-dioxide layer. The isolating structure is formed by a trench filled with a dielectric material.Type: ApplicationFiled: May 30, 2012Publication date: December 6, 2012Applicant: STMICROELECTRONICS (CROLLES 2) SASInventors: Francois Roy, Francois Leverd, Jens Prima
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Publication number: 20110108939Abstract: A method for manufacturing a back-side illuminated image sensor, including the steps of: forming, inside and on top of an SOI-type silicon layer, components for trapping and transferring photogenerated carriers and isolation regions; forming a stack of interconnection levels on the silicon layer and attaching, on the interconnect stack, a semiconductor handle; removing the semiconductor support; forming, in the insulating layer and the silicon layer, trenches reaching the isolation regions; depositing a doped amorphous silicon layer, more heavily doped than the silicon layer, at least on the walls and the bottom of the trenches and having the amorphous silicon layer crystallize; and filling the trenches with a reflective material.Type: ApplicationFiled: November 9, 2010Publication date: May 12, 2011Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SAInventors: Michel Marty, François Leverd
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Patent number: 7456071Abstract: An integrated circuit including a buried layer of determined conductivity type in a plane substantially parallel to the plane of a main circuit surface, in which the median portion of this buried layer is filled with a metal-type material.Type: GrantFiled: May 6, 2005Date of Patent: November 25, 2008Assignee: STMicroelectronics S.A.Inventors: Michel Marty, Philippe Coronel, François Leverd
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Patent number: 7214597Abstract: A method is provided for fabricating integrated electronic components. According to the method, an initial structure is produced on the surface of a first substrate. This initial structure incorporates a defined pattern formed from volumes of differentiated materials. At least part of the initial substrate that includes the defined pattern is transferred onto a second substrate, preferably by inverting the first substrate against the second substrate and then removing the first substrate. An additional structure is then produced on the second substrate. This additional structure includes volumes of material placed in correspondence with some of the volumes of differentiated material of the defined pattern. The electronic components thus produced may have a suitable configuration in accordance with technological or geometrical constraints.Type: GrantFiled: April 23, 2003Date of Patent: May 8, 2007Assignee: STMicroelectronics S.A.Inventors: Philippe Coronel, Francois Leverd, Thomas Skotnicki
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Publication number: 20050191818Abstract: An integrated circuit including a buried layer of determined conductivity type in a plane substantially parallel to the plane of a main circuit surface, in which the median portion of this buried layer is filled with a metal-type material.Type: ApplicationFiled: May 6, 2005Publication date: September 1, 2005Applicant: STMicroelectronics, S.A.Inventors: Michel Marty, Philippe Coronel, Francois Leverd
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Patent number: 6828646Abstract: An isolation trench formed in a semiconductor substrate has side walls and a bottom wall. Spacers are on the side walls and face each other for forming a narrow channel therebetween. The bottom wall and the spacers are coated with an electrically insulating material for delimiting a closed empty cavity in the channel. The isolation trench is applicable to the manufacture of integrated circuits.Type: GrantFiled: October 16, 2002Date of Patent: December 7, 2004Assignee: STMicroelectronics SAInventors: Michel Marty, Francois Leverd, Philippe Coronel, Joaquin Torres
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Publication number: 20040145058Abstract: A method for manufacturing buried connections in an integrated circuit, including the steps of: providing a structure formed of a first support wafer glued at the rear surface of a thin semiconductor wafer, one or several elements of the integrated circuit being possibly formed in and above the thin wafer; gluing a second support wafer on the structure on the front surface side of the thin wafer; removing the first support wafer; forming connections between different areas of the rear surface of the thin wafer; gluing a third support wafer on the connections; and removing the second support wafer.Type: ApplicationFiled: December 12, 2003Publication date: July 29, 2004Inventors: Michel Marty, Francois Leverd, Philippe Coronel
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Patent number: 6759304Abstract: The invention relates to a DRAM integration method that does away with the alignment margins inherent to the photoetching step of the upper electrode of the capacitance for inserting the bit line contact. The removal of the upper electrode is self-aligned on the lower electrode of the capacitance. This is accomplished by forming a difference in topography at the point where the opening of the upper electrode is to be made, and depositing a non-doped polysilicon layer on the upper electrode. An implantation of dopants is performed on this layer, and the part of the non-doped layer located in the lower part of the zone showing the difference in topography is selectively etched. The remainder of the polysilicon layer and the part of the upper electrode located in the lower layer are also etched.Type: GrantFiled: January 9, 2002Date of Patent: July 6, 2004Assignee: STMicroelectronics SAInventors: Philippe Coronel, Marc Piazza, François Leverd
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Publication number: 20040104448Abstract: An integrated circuit including a buried layer of determined conductivity type in a plane substantially parallel to the plane of a main circuit surface, in which the median portion of this buried layer is filled with a metal-type material.Type: ApplicationFiled: October 3, 2003Publication date: June 3, 2004Inventors: Michel Marty, Philippe Coronel, Francois Leverd
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Publication number: 20040033676Abstract: A method is provided for fabricating integrated electronic components. According to the method, an initial structure is produced on the surface of a first substrate. This initial structure incorporates a defined pattern formed from volumes of differentiated materials. At least part of the initial substrate that includes the defined pattern is transferred onto a second substrate, preferably by inverting the first substrate against the second substrate and then removing the first substrate. An additional structure is then produced on the second substrate. This additional structure includes volumes of material placed in correspondence with some of the volumes of differentiated material of the defined pattern. The electronic components thus produced may have a suitable configuration in accordance with technological or geometrical constraints.Type: ApplicationFiled: April 23, 2003Publication date: February 19, 2004Applicant: STMICROELECTRONICS S.A.Inventors: Philippe Coronel, Francois Leverd, Thomas Skotnicki