Abstract: The present invention relates to an etching composition, in particular, for silicon materials, a method for characterizing defects on surfaces of such materials and a process of treating such surfaces with the etching composition, wherein the etching composition comprises an organic oxidant dissolved in a solvent, and a deoxidant, wherein the deoxidant comprises HF or HBF4 or mixtures thereof.

Abstract: The invention relates to a method for forming a plurality of electrically conductive islands in a working layer of a multilayer structure made from semiconductor materials, with the structure including an electrically insulating layer located beneath the working layer. This method includes the steps of selectively masking certain regions of the working layer in order to define several islands therein, with each region masked from the working layer corresponding to a respective island, and then wet chemical etching of the masked working layer to form a plurality of working layer islands each surrounded by the electrically insulating layer. The invention also proposes the application of such a method to the characterization of the electrical properties of a structure, and an associated device.

Abstract: The invention provides methods for reducing trap densities at interfaces in a multilayer semiconductor wafer, specifically trap densities between an active layer and an insulating layer under the active layer. The methods comprise exposing wafers to high temperatures in a generally neutral atmosphere that also comprises one or more species that can, or whose ions can, migrate into the wafer down to the interface where reduction of the trap density is desired.

Abstract: The invention relates to a process for manufacturing a multilayer structure made from semiconducting materials that include an active layer, a support layer and an electrically insulating layer between the active layer and the support layer. The process includes the step of modifying the density of carrier traps or the electrical charge within the electrically insulating layer in order to minimize electrical losses in the structure support layer.

Abstract: The invention provides methods for reducing trap densities at interfaces in a multilayer semiconductor wafer, specifically trap densities between an active layer and an insulating layer under the active layer. The methods comprise exposing wafers to high temperatures in a generally neutral atmosphere that also comprises one or more species that can, or whose ions can, migrate into the wafer down to the interface where reduction of the trap density is desired.

Abstract: The invention relates to a method for forming a plurality of electrically conductive islands in a working layer of a multilayer structure made from semiconductor materials, with the structure including an electrically insulating layer located beneath the working layer. This method includes the steps of selectively masking certain regions of the working layer in order to define several islands therein, with each region masked from the working layer corresponding to a respective island, and then wet chemical etching of the masked working layer to form a plurality of working layer islands each surrounded by the electrically insulating layer. The invention also proposes the application of such a method to the characterization of the electrical properties of a structure, and an associated device.

Abstract: The invention relates to a process for manufacturing a multilayer structure made from semiconducting materials that include an active layer, a support layer and an electrically insulating layer between the active layer and the support layer. The process includes the step of modifying the density of carrier traps or the electrical charge within the electrically insulating layer in order to minimize electrical losses in the structure support layer.