Abstract: Methods and systems are provided for an electric heavy-duty vehicle. In one example, the vehicle includes a battery pack for supplying current to an electric motor of the vehicle, the battery pack arranged in a chassis of the vehicle and configured to form part of a floor of the vehicle. The vehicle also includes a motor coupled to front wheels of the vehicle, the front wheels having hub assemblies housing drive shaft adapters configured to permanently couple the hub assemblies to drive shafts of the front wheels, and a cradle configured to be mounted with electrical sub-systems of the vehicle.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to multi-channel transistors and methods of manufacture. The structure includes: a gate structure; a single channel layer in a channel region under the gate structure; a drift region adjacent to the gate structure; and multiple channel layers in the drift region coupled to the single channel layer under the gate structure.

Abstract: Structures for a transistor and methods of forming a structure for a transistor. The structure comprises a semiconductor substrate including a top surface and a trench, a gate electrode disposed in the trench, a first doped region disposed beneath the trench, a first contact coupled to the first doped region, a second doped region disposed in a vertical direction between the first doped region and the top surface, and a plurality of second contacts coupled to the second doped region. The semiconductor substrate comprises a wide bandgap semiconductor material. The first contact extends in the semiconductor substrate from the top surface to a first depth that adjoins the first doped region. The plurality of second contacts extend in the semiconductor substrate from the top surface to a second depth that adjoins the second doped region, and the second depth is less than the first depth.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor substrate comprising a wide bandgap semiconductor material, a gate electrode, a first gate dielectric layer disposed on the semiconductor substrate, and a second gate dielectric layer disposed between the first gate dielectric layer and the gate electrode.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The method comprises cleaning a surface of a semiconductor substrate with atomic layer etching. The semiconductor substrate comprises a wide bandgap semiconductor material. The method further comprises forming a gate dielectric layer on the surface of the semiconductor substrate.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor substrate including a first doped region, a second doped region, a third doped region, and a trench that includes a trench bottom, a first sidewall, and a second sidewall opposite to the first sidewall. The first doped region is disposed adjacent to the first sidewall of the trench, the second doped region is disposed adjacent to the second sidewall of the trench, the third doped region is disposed adjacent to the trench bottom of the trench. The third doped region connects the first doped region to the second doped region, and the first doped region, the second doped region, and the third doped region have a conductivity type. The structure further comprises a gate structure in the trench.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor substrate including a top surface, a doped region adjacent to the top surface, and a trench that extends through the doped region. The semiconductor substrate comprises a wide bandgap semiconductor material. The structure further comprises a gate structure including a gate conductor layer in the trench, and a dielectric layer on the top surface of the semiconductor substrate. The dielectric layer includes an opening that is aligned with the trench in the semiconductor substrate, and the dielectric layer comprises a material with a melting point that is greater than or equal to 2000° C.

Abstract: Structures for a field-effect transistor and methods of forming such structures. The structure comprises a semiconductor substrate including a top surface, a doped region adjacent to the top surface, and a trench that extends through the doped region. The semiconductor substrate comprises a wide bandgap semiconductor material. The structure further comprises a gate structure including a gate conductor layer. The gate conductor layer has a first portion disposed above the top surface of the semiconductor substrate and a second portion disposed inside the trench below the top surface of the semiconductor substrate.

Abstract: Systems and methods are disclosed for performing operations comprising: receiving a plurality of training medical images used to train a machine learning technique; applying a model to the plurality of training medical images to generate a distribution representation of the plurality of training medical images; computing a first distance between a given training medical image in the plurality of training medical images and the distribution representation; computing a second distance between a new medical image and the distribution representation; and computing a quality factor indicating a measure of similarity between a new medical image and the plurality of medical images as a function of the first distance and the second distance.

Abstract: Systems and methods are disclosed for performing operations comprising: receiving a plurality of training images representing different phases of a periodic motion of a target region in a patient; applying a model to the plurality of training images to generate a lower-dimensional feature space representation of the plurality of training images; clustering the lower-dimensional feature space representation of the plurality of training images into a plurality of groups corresponding to the different phases of the periodic motion; and classifying a motion phase associated with a new image of the target region in the patient based on the plurality of groups of the clustered lower-dimensional feature space representation of the plurality of training images.

Abstract: Structures for a junction field-effect transistor and methods of forming such structures. The structure comprises a semiconductor substrate including a trench, and a source including a doped region in the semiconductor substrate adjacent to the trench. The doped region and the semiconductor substrate have the same conductivity type. The doped region has a first boundary adjacent to a surface of the semiconductor substrate and a second boundary spaced in depth from the first boundary. The structure further comprises a gate structure including a conductor layer inside the trench and a dielectric layer inside the trench. The first conductor layer has a surface positioned between the first boundary of the doped region and the second boundary of the doped region, and the dielectric layer is positioned on the surface of the conductor layer.

Abstract: A structure for an III-V integrated circuit includes an integrated depletion and enhancement mode gallium nitride high electron mobility transistors (HEMTs). The structure includes a first, depletion mode HEMT having a first source, a first drain and a first fieldplate gate between the first source and the first drain, and a second, enhancement mode HEMT having a second source and a second drain. The second HEMT also includes a gallium nitride (GaN) gate and a second fieldplate gate between the second source and the second drain. The second fieldplate gate of the second HEMT may be closer to the second drain than the GaN gate. The structure provides a reliable, low leakage, high voltage depletion mode HEMT (e.g., with operating voltages of greater than 100V, but with a pinch-off voltage of less than 6 Volts) integrated with a gallium nitride (GaN) gate-based enhancement mode HEMT.

Abstract: Structures including compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure comprises a layer stack on a substrate, a conductive contact extending in a vertical direction fully through the layer stack to the substrate, and a device structure including a source ohmic contact and a drain ohmic contact. The layer stack including a plurality of semiconductor layers each comprising a compound semiconductor material, the conductive contact is arranged in the layer stack to separate a first portion of the layer stack from a second portion of the layer stack, and the source ohmic contact and the drain ohmic contact have a contacting relationship with at least one of the plurality of semiconductor layers of the first portion of the layer stack.

Abstract: Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.

Abstract: Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.

Abstract: Structures for a bidirectional switch and methods of forming such structures. A substrate contact is formed in a trench defined in a substrate. A substrate includes a trench and a substrate contact in the trench. A bidirectional switch, which is on the substrate, includes a first source/drain electrode, a second source/drain electrode, an extension region between the first source/drain electrode and the second source/drain electrode, and a gate structure. A substrate-bias switch, which is on the substrate, includes a gate structure, a first source/drain electrode coupled to the substrate contact, a second source/drain electrode coupled to the first source/drain electrode of the bidirectional switch, and an extension region laterally between the gate structure and the first source/drain electrode.

Abstract: Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.

Abstract: A method for controlling a laser profiler, the laser profiler being configured for generating a laser line on a surface to be inspected, the method comprising: receiving an image of the laser line; determining an actual intensity of the laser line; calculating an amplification factor for the laser line based on the actual intensity of the laser line, a target intensity for the laser line, a power of the laser, a camera gain of the camera and an exposure time of the laser line on the surface to be inspected, the amplification factor allowing the actual intensity of the laser line to reach the target intensity while minimizing the power of the laser; and based on the calculated amplification factor, adjusting at least one parameter of the laser profiler so that the actual intensity of the laser line corresponds to the target intensity.

Abstract: Systems and methods are disclosed for performing operations comprising: receiving a plurality of training images representing different phases of a periodic motion of a target region in a patient; applying a model to the plurality of training images to generate a lower-dimensional feature space representation of the plurality of training images; clustering the lower-dimensional feature space representation of the plurality of training images into a plurality of groups corresponding to the different phases of the periodic motion; and classifying a motion phase associated with a new image of the target region in the patient based on the plurality of groups of the clustered lower-dimensional feature space representation of the plurality of training images.

Abstract: Structures for a bidirectional switch and methods of forming such structures. A substrate contact is formed in a trench defined in a substrate. A substrate includes a trench and a substrate contact in the trench. A bidirectional switch, which is on the substrate, includes a first source/drain electrode, a second source/drain electrode, an extension region between the first source/drain electrode and the second source/drain electrode, and a gate structure. A substrate-bias switch, which is on the substrate, includes a gate structure, a first source/drain electrode coupled to the substrate contact, a second source/drain electrode coupled to the first source/drain electrode of the bidirectional switch, and an extension region laterally between the gate structure and the first source/drain electrode.