Patents by Inventor François Labonté

François Labonté has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170237663
    Abstract: A method and apparatus of a device that determines a match for a destination address using an exact match table and a longest prefix match table of a network element is described. In an exemplary embodiment, the network element receives a data packet that includes a destination address. The network element generates a key for the destination address, wherein the key represents more addresses than the destination address. The network element further performs an address lookup using the key in an exact match table. Furthermore, a match in the address lookup indicates a first transmitting interface of the network element. The network element additionally performs an address lookup using the destination address with a longest prefix match table, wherein a match in the address lookup indicates a second transmitting interface of the network element.
    Type: Application
    Filed: May 2, 2017
    Publication date: August 17, 2017
    Inventors: Francois Labonte, Hugh W. Holbrook
  • Publication number: 20170237662
    Abstract: A method and apparatus of a device that determines a match for a destination address using an exact match table and a longest prefix match table of a network element is described. In an exemplary embodiment, the network element receives a data packet that includes a destination address. The network element generates a key for the destination address, wherein the key represents more addresses than the destination address. The network element further performs an address lookup using the key in an exact match table. Furthermore, a match in the address lookup indicates a first transmitting interface of the network element. The network element additionally performs an address lookup using the destination address with a longest prefix match table, wherein a match in the address lookup indicates a second transmitting interface of the network element.
    Type: Application
    Filed: May 2, 2017
    Publication date: August 17, 2017
    Inventors: Francois Labonte, Hugh W. Holbrook
  • Patent number: 9729460
    Abstract: A method for managing port bandwidth in network devices. The method includes determining a first and a second ingress bandwidth of a first and a second network chip, respectively, determining an egress bandwidth of an egress port of a third network chip, determining a first and a second weight for the first and the second network chip, respectively, where the first and the second weight are determined based on a bandwidth including the first and second ingress bandwidth, processing a first data packet, received by a first ingress port administrated by the first network chip, based on the first weight and the egress bandwidth, and processing a second data packet, received by a second ingress port administrated by the second network chip, based on the second weight, and the egress bandwidth, where the destination of the first and the second data packet is the egress port.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: August 8, 2017
    Assignee: Arista Networks, Inc.
    Inventors: François Labonte, Muhammad Yousuf
  • Publication number: 20170222881
    Abstract: Various embodiments of a network element comprising a control plane including stream tracer logic are described herein. The network element additionally includes a data plane coupled to the control plane, where the data plane includes forwarding logic to forward a unit of network data from an ingress interface to an egress interface. The stream tracer logic can be configured to cause marking logic to mark selected units of network data for to be counted by counting logic and to cause the counting logic to count marked units of network data. The stream tracer logic can determine whether units of network data are dropped within the forwarding logic via comparison of an ingress count of the marked units of network data with an egress count of the marked units of network data.
    Type: Application
    Filed: December 14, 2016
    Publication date: August 3, 2017
    Inventors: Hugh Holbrook, Francois Labonte, Kenneth Duda
  • Patent number: 9680749
    Abstract: A method and apparatus of a device that determines a match for a destination address using an exact match table and a longest prefix match table of a network element is described. In an exemplary embodiment, the network element receives a data packet that includes a destination address. The network element generates a key for the destination address, wherein the key represents more addresses than the destination address. The network element further performs an address lookup using the key in an exact match table. Furthermore, a match in the address lookup indicates a first transmitting interface of the network element. The network element additionally performs an address lookup using the destination address with a longest prefix match table, wherein a match in the address lookup indicates a second transmitting interface of the network element.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: June 13, 2017
    Assignee: Arista Networks, Inc.
    Inventors: Francois Labonte, Hugh W. Holbrook
  • Patent number: 9548892
    Abstract: A method for configuring network devices. The method includes selecting a first hash function to use to process packets using Equal-Cost Multi-Path (ECMP) on a network device, where the first hash function is selected from a set of hash functions using a second hash function, a network chip ID of the network chip in the network device, a network device media access control (MAC) address, and an ECMP flag. The method further includes selecting a third hash function to use to process packets using a Link Aggregation Group (LAG), where the third hash function is selected from the set of hash functions using a fourth hash function, the network chip ID of the network chip in the network device, the network device MAC address, and the LAG flag. The method further includes processing a packet received by the network device using the first hash function or the third hash function.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: January 17, 2017
    Assignee: Arista Networks, Inc.
    Inventors: François Labonte, Hugh W. Holbrook
  • Publication number: 20170005951
    Abstract: Various embodiments of a virtual output queue system within a network element enables per-input port virtual output queues within a network data processor of the network element. In one embodiment, each port managed by a network data processor has an associated set of virtual output queues for each output port on the network data element. In one embodiment, network data processor hardware supports per-processor VOQs and per-input port VOQs are enabled in hardware for layer 3 forwarding by overloading layer 2 forwarding logic. In such embodiment, a mapping table is generated to enable virtual per-input port VOQs for layer 3 forwarding logic using layer 2 logic that is otherwise unused during layer 3 forwarding. In one embodiment, multiple traffic classes can be managed per-input port when using per-input port VOQs. In one embodiment, equal cost multi-path (ECMP) and link aggregation support is also enabled.
    Type: Application
    Filed: January 6, 2016
    Publication date: January 5, 2017
    Inventors: Francois Labonte, Aditya Vikram Daga
  • Publication number: 20160301618
    Abstract: A method for managing port bandwidth in network devices. The method includes determining a first and a second ingress bandwidth of a first and a second network chip, respectively, determining an egress bandwidth of an egress port of a third network chip, determining a first and a second weight for the first and the second network chip, respectively, where the first and the second weight are determined based on a bandwidth including the first and second ingress bandwidth, processing a first data packet, received by a first ingress port administrated by the first network chip, based on the first weight and the egress bandwidth, and processing a second data packet, received by a second ingress port administrated by the second network chip, based on the second weight, and the egress bandwidth, where the destination of the first and the second data packet is the egress port.
    Type: Application
    Filed: April 13, 2015
    Publication date: October 13, 2016
    Inventors: François Labonte, Muhammad Yousuf
  • Publication number: 20160254999
    Abstract: A method and apparatus of a device that determines a match for a destination address using an exact match table and a longest prefix match table of a network element is described. In an exemplary embodiment, the network element receives a data packet that includes a destination address. The network element generates a key for the destination address, wherein the key represents more addresses than the destination address. The network element further performs an address lookup using the key in an exact match table. Furthermore, a match in the address lookup indicates a first transmitting interface of the network element. The network element additionally performs an address lookup using the destination address with a longest prefix match table, wherein a match in the address lookup indicates a second transmitting interface of the network element.
    Type: Application
    Filed: May 28, 2015
    Publication date: September 1, 2016
    Inventors: Francois Labonte, Hugh W. Holbrook
  • Publication number: 20160218916
    Abstract: A method for configuring network devices. The method includes selecting a first hash function to use to process packets using Equal-Cost Multi-Path (ECMP) on a network device, where the first hash function is selected from a set of hash functions using a second hash function, a network chip ID of the network chip in the network device, a network device media access control (MAC) address, and an ECMP flag. The method further includes selecting a third hash function to use to process packets using a Link Aggregation Group (LAG), where the third hash function is selected from the set of hash functions using a fourth hash function, the network chip ID of the network chip in the network device, the network device MAC address, and the LAG flag. The method further includes processing a packet received by the network device using the first hash function or the third hash function.
    Type: Application
    Filed: January 26, 2015
    Publication date: July 28, 2016
    Inventors: François Labonte, Hugh W. Holbrook
  • Patent number: 9395748
    Abstract: A method for distributing time information in network devices. The method includes sending a first clock signal from a first system control device (SCD) to a PLL chip, sending a first time of day (TOD) from the first SCD to a line card system control device (LC-SCD), sending a second clock signal from a second SCD to the PLL chip and sending a second TOD from the second SCD to the LC-SCD. The method further includes synchronizing a third clock signal, generated by the PLL chip, to the first clock signal, if the first SCD is operational. The method further includes sending the third clock signal to a network chip, deriving, using the third clock signal, a first network-chip-internal clock signal and applying the first network-chip-internal clock signal to increment a network-chip-internal TOD to obtain a third TOD. The method further includes synchronizing the third TOD to the first TOD.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: July 19, 2016
    Assignee: Arista Networks, Inc.
    Inventors: François Labonte, Deepak Sebastian
  • Publication number: 20160182372
    Abstract: A method and apparatus of a device that determines a match for a compressed address using an exact match table of a network element is described. In an exemplary embodiment, the network element receives a data packet that has a destination address. The network element further compresses the destination address to give a compressed address. In addition, the network element performs an address lookup using the compressed address in an exact match table. Furthermore, a match in the address lookup indicates a transmitting interface of the network element. The network element forwards the data packet using the transmitting interface.
    Type: Application
    Filed: May 12, 2015
    Publication date: June 23, 2016
    Inventors: Hugh W. Holbrook, Francois Labonte, Eitan Joffe
  • Patent number: 6966019
    Abstract: An automatic test system transfers measure data from one or more test instruments to a processor and processes the measure data, the packaging, transfer, and the processing of the measure data initiated by the one or more test instruments. A method for testing a device under test includes capturing measure data with a test instrument, and initiating, with the test instrument, operation upon the measure data. The operations include packaging the measure data to provide packaged data, and transferring the packaged data to a switching/processing circuit for processing. A method of manufacturing an electronic circuit includes fabricating the electronic circuit and testing the electronic circuit with the aforementioned method.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: November 15, 2005
    Assignee: Teradyne, Inc.
    Inventors: Dominic Viens, Gregory P. Brown, Larry Klein, Francois Labonte
  • Publication number: 20040003328
    Abstract: An automatic test system transfers measure data from one or more test instruments to a processor and processes the measure data, the packaging, transfer, and the processing of the measure data initiated by the one or more test instruments. A method for testing a device under test includes capturing measure data with a test instrument, and initiating, with the test instrument, operation upon the measure data. The operations include packaging the measure data to provide packaged data, and transferring the packaged data to a switching/processing circuit for processing. A method of manufacturing an electronic circuit includes fabricating the electronic circuit and testing the electronic circuit with the aforementioned method.
    Type: Application
    Filed: June 28, 2002
    Publication date: January 1, 2004
    Inventors: Dominic Viens, Gregory P. Brown, Larry Klein, Francois Labonte