Patents by Inventor François LEFLOCH

François LEFLOCH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240341201
    Abstract: A method for making a device with superconductor qubit(s) including at least one JoFET formed by the following steps of: making, over a semiconductor layer, a protective dielectric portion arranged over a first region of the semiconductor layer; implanting dopants in second regions adjacent to the first region; depositing a protective dielectric layer covering the protective dielectric portion and the second regions; exposing the protective dielectric layer to a laser pulse; and wherein the materials and the thicknesses of the protective dielectric portion and of the protective dielectric layer are selected so as to prevent the laser pulse from reaching the first region, and melting the semiconductor of the second regions which forms, after cooling, a recrystallised semiconductor material having superconductor material properties.
    Type: Application
    Filed: April 21, 2023
    Publication date: October 10, 2024
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Cyrille LE ROYER, Fabrice NEMOUCHI, Nicolas POSSEME, Sébastien KERDILES, François LEFLOCH
  • Publication number: 20240268239
    Abstract: Method for producing a superconducting transistor comprising: producing a dummy gate on a first part of a semiconducting layer; producing superconducting electrodes such that the first part of the semiconducting layer comprises sides edges arranged against parts of the superconducting electrodes, and comprising a deposition of a superconducting material layer having first parts arranged against side edges of the dummy gate and second parts forming parts of the superconducting electrodes; producing lateral spacers next to the first parts of the superconducting material layer and on the second parts of the superconducting material layer; removing the dummy gate and the first parts of the superconducting material layer, creating a gate location arranged between the lateral spacers and above the first part of the semiconducting layer and above said parts of the superconducting electrodes; producing a gate in the gate location.
    Type: Application
    Filed: February 1, 2024
    Publication date: August 8, 2024
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Fabrice NEMOUCHI, Francois LEFLOCH, Shi-Li ZHANG, Zhen ZHANG
  • Patent number: 11941485
    Abstract: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: March 26, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Louis Hutin, Cyrille Le Royer, François Lefloch, Fabrice Nemouchi, Maud Vinet
  • Publication number: 20230186136
    Abstract: A method for producing a quantum device comprising forming a supraconductive layer, forming a mask on the supraconductive layer, the mask comprising masking patterns and at least two openings alternately in a direction, the at least two openings being separated from one another by a separation distance pi (i=1 . . . n), and further each having a width di (i=1 . . . n+1), such as the separation distance pi and a width di are less than a coherence length of a Cooper pair in said supraconductive material, and modifying, through the at least two openings, of the exposed portions of the supraconductive layer, so as to form at least two barriers of width di separating the supraconductive regions.
    Type: Application
    Filed: November 21, 2022
    Publication date: June 15, 2023
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Cyrille LE ROYER, François LEFLOCH, Fabrice NEMOUCHI, Nicolas POSSEME
  • Patent number: 11631739
    Abstract: A method for producing a transistor includes producing on a substrate provided with a semiconductor surface layer in which an active area can be formed, a gate block arranged on the active area. Lateral protection areas are formed against lateral faces of the gate block. Source and drain regions based on a metal material-semiconductor material compound are formed on either side of the gate and in the continuation of a portion located facing the gate block. Insulating spacers are formed on either side of the gate resting on the regions based on a metal material-semiconductor material compound.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 18, 2023
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Fabrice Nemouchi, Antonio Lacerda Santos Neto, Francois Lefloch
  • Publication number: 20230060817
    Abstract: A Josephson transistor, this transistor comprising a source and a drain each comprising an electric charge reservoir in electrical contact with a semiconductor layer. Each reservoir comprises a lower face and a side face both buried inside the semiconductor layer, The lower face of each reservoir extends mainly in an intermediate plane parallel to the plane of a support, this intermediate plane being located between a lower plane and an upper plane that define the semiconductor layer. The side face of each reservoir extends mainly perpendicular to the plane of the support, this side face facing the corresponding side face of the other reservoir and being separated from this corresponding side face of the other reservoir by a channel located under a gate of this transistor.
    Type: Application
    Filed: August 30, 2022
    Publication date: March 2, 2023
    Applicants: Commissariat à l'Energie Atomique et aux Energies Alternatives, UNIVERSITE GRENOBLE ALPES
    Inventors: Fabrice NEMOUCHI, Frederic GUSTAVO, François LEFLOCH, Tom VETHAAK
  • Publication number: 20230061391
    Abstract: A method for producing a superconducting vanadium silicide on a silicon layer includes treating a face of the silicon layer in order to prepare it for a deposition of vanadium silicide, then depositing a vanadium silicide layer on the prepared face of the silicon layer in order to obtain a stack of a vanadium silicide layer directly deposited on the silicon layer, then an annealing the stack which increases the critical temperature of the vanadium silicide deposited. The treating includes an operation of incorporation of argon atoms in the silicon layer through the face of the silicon layer.
    Type: Application
    Filed: August 31, 2022
    Publication date: March 2, 2023
    Applicants: Commissariat á l'Energie Atomique et aux Energies Alternatives, UNIVERSITE GRENOBLE ALPES
    Inventors: Fabrice NEMOUCHI, Thierry FARJOT, Frédéric GUSTAVO, François LEFLOCH, Tom Doekle VETHAAK
  • Publication number: 20220172093
    Abstract: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.
    Type: Application
    Filed: November 24, 2021
    Publication date: June 2, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas POSSEME, Louis HUTIN, Cyrille LE ROYER, François LEFLOCH, Fabrice NEMOUCHI, Maud VINET
  • Publication number: 20220173229
    Abstract: A quantum device includes a transistor pattern carried by a substrate, the transistor pattern having, in a stack, a gate dielectric and a superconducting gate on the gate dielectric. The superconducting gate has a base, a tip, sidewalls and at least one superconducting region made of a material that has, as a main component, at least one superconducting element. The superconducting gate also includes a basal portion having a dimension, taken in a first direction of a basal plane that is smaller than a dimension of the tip of the superconducting gate. The transistor pattern further includes at least one dielectric portion made of a dielectric material in contact with the top face of the gate dielectric and the basal portion of the superconducting gate.
    Type: Application
    Filed: November 24, 2021
    Publication date: June 2, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas POSSEME, Louis HUTIN, Cyrille LE ROYER, François LEFLOCH, Fabrice NEMOUCHI, Maud VINET
  • Publication number: 20200161422
    Abstract: Production of a transistor comprising: producing, on a substrate provided with a semiconductor surface layer (4) wherein an active area (4a) is capable of being formed: a gate block (9) arranged on this active area, forming lateral protection areas (15c) against lateral faces of said gate block (9), forming source and drain regions (19a, 19b) being based on a metal material-semiconductor material compound on either side of the gate and in the continuation of a portion located facing the gate block, then forming insulating spacers (23c) on either side of the gate and resting on said regions based on a metal material-semiconductor material compound (FIG. 1G).
    Type: Application
    Filed: November 13, 2019
    Publication date: May 21, 2020
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Fabrice Nemouchi, Antonio Lacerda Santos Neto, Francois Lefloch