Abstract: A coherent receiver includes a receive signal path including i) an input configured to connect a receive signal, ii) one or more signal paths connected to the input and to one or more optical hybrids, and iii) a variable optical attenuator (VOA) in each of the one or more signal paths; and a local oscillator (LO) signal path including i) an input configured to connect to an LO and the one or more optical hybrids, and ii) one or more complementary VOAs located between the input and the one or more optical hybrids, wherein the one or more complementary VOAs are configured to cancel any phase changes from the VOA in each of the one or more signal paths. The VOA in each of the one or more signal paths and the one or more complementary VOAs can be p-i-n junctions.

Abstract: A circuit interconnection structure has a cavity formed through an entire thickness between first and second surfaces. A first integrated circuit is mounted on the first surface. A device carrier comprises a first portion that fits within at least a portion of the cavity. A second portion of the device carrier rigidly connected to the first portion of the device carrier is attached to the first surface. A device positioned within the first portion of the device carrier and mounted to a mounting surface of the device carrier is substantially parallel to the first surface. The device comprises a second integrated circuit. A total thermal expansion of the device carrier between the second portion of the device carrier and the mounting surface is substantially equal to a total thermal expansion of the device between the second integrated circuit and the portion of the device mounted to the mounting surface.

Abstract: An article of manufacture comprises: at least a portion of a wafer comprising a substate and one or more layers fabricated on the substrate; one or more integrated photonic structures in the portion of the wafer, where at least a first integrated photonic structure of the one or more integrated photonic structures is associated with an electromagnetic wave propagation region that extends beyond a first surface of a first layer of the one or more layers; an array of structures arranged in a two-dimensional pattern on a portion of the first surface; and an adhesive material making contact with the first surface and with at least a majority of the structures in the array of structures.

Abstract: The proposed approach deals with efficient transmission for distributed AI with a provision to switch among multiple bandwidths. During the distributed inference at edge devices, each device needs to load part of the AI model only once, but the input/output features communicated between them can be flexibly configured depending on the available transmission bandwidth by enabling/disabling connection between nodes in the Dynamic feature size Switch (DySw). When some nodes are connected or disconnected in order to achieve the desired compression factor, other parameters of the DNN remain the same. That is, the same DNN model is used for different compression factors, and no new DNN model needs to be downloaded to adapt to the compression factor or the network bandwidth.

Abstract: An apparatus for securing a wafer, the wafer having a first side comprising a plurality of fabricated structure regions and a second side that has at least one region that is exposed for fabrication when the wafer is secured, comprises: a carrier base configured to receive the wafer, the carrier base comprising one or more alignment features for aligning the wafer to the carrier base; and a plurality of support structures arranged on the carrier base. Three or more of the support structures are each configured to contact the first side of the wafer when the wafer is secured to the carrier base, and arranged on the carrier base to contact the first side of the wafer at a location on the first side of the wafer that is between at least two of the plurality of fabricated structure regions.

Abstract: Aspects of the subject disclosure may include, for example, a process that provides a semiconductor substrate and forms repeating, conductive patterns configured for coupling to active circuitry. Each pattern comprises a group of thermally conductive layers, wherein the group of thermally layers is thermally coupled to a thermal source generated by the active circuitry. Thermally conductive vias interconnect the group of thermally conductive layers, wherein a combination of the vias and the group of thermally conductive layers is configured to transfer heat from the thermal source with a desired directionality. The first repeating patterns are thermally coupled to each other to combine the desired directionality of each of the patterns, wherein the combination results in a distributed directionality of the heat from the thermal source thereby reducing a localized concentration of the heat. Other embodiments are disclosed.

Abstract: Systems and methods provide optical referencing in an optical system including a plurality of optical devices with variable perturbative drift rates. A method includes, subsequent to determining a tuning rate of one or more interrogator devices, which are tunable, and subsequent to locking the plurality of optical devices including the one or more interrogator devices, detecting a drift in spectrum of the optical system based on a perturbation; and tracking the drift based on variable perturbative drift rates of each of the plurality of optical devices which are each exposed to the perturbation.

Abstract: A coherent receiver includes a receive signal path including i) an input configured to connect a receive signal, ii) one or more signal paths connected to the input and to one or more optical hybrids, and iii) a variable optical attenuator (VOA) in each of the one or more signal paths; and a local oscillator (LO) signal path including i) an input configured to connect to an LO and the one or more optical hybrids, and ii) one or more complementary VOAs located between the input and the one or more optical hybrids, wherein the one or more complementary VOAs are configured to cancel any phase changes from the VOA in each of the one or more signal paths. The VOA in each of the one or more signal paths and the one or more complementary VOAs can be p-i-n junctions.

Abstract: A method including disposing a structural adhesive onto an elevated surface of a first chip that includes a cavity disposed below the elevated surface. The method includes contacting a carrier with the structural adhesive. The carrier includes a second chip that optically aligns with a lateral surface of the cavity. The method includes curing the structural adhesive so that the carrier and host chip are mechanically anchored. An apparatus includes a first chip including a cavity located between lateral walls of the first chip and a carrier mechanically anchored with the first chip at a top portion of the lateral walls. The carrier includes a second chip that optically aligns with the first chip at a side portion of one of the lateral walls. The first and second chips are free of contact at a bottom surface of the second chip and a bottom surface of the cavity.

Abstract: At least a portion of an integrated circuit wafer includes at least one layer in which two or more waveguides are formed. A cavity is formed in the integrated circuit wafer. At least one die, comprising a photonic integrated circuit, has: at least one edge on which there are two or more optical mode defining structures in proximity to respective optical mode defining structures on at least one surface of the cavity, a bottom surface secured to a bottom surface of the cavity, and a top surface on which there is at least one metal contact.

Abstract: At least a portion of an integrated circuit wafer includes at least one layer in which two or more waveguides are formed. A cavity is formed in the integrated circuit wafer. At least one die, comprising a photonic integrated circuit, has: at least one edge on which there are two or more optical mode defining structures in proximity to respective optical mode defining structures on at least one surface of the cavity, a bottom surface secured to a bottom surface of the cavity, and a top surface on which there is at least one metal contact.

Abstract: One or more photonic structures are formed within one or more layers over a surface of a substrate, and multiple trenches are formed through the one or more layers housing devices coupled to one or more of the photonic structures. The trenches may include: a first trench that has a bottom surface within the substrate that has a first surface topology characterized by a first surface roughness at a first depth within the substrate relative to the surface of the substrate, and a second trench that has a bottom surface within the substrate that has a second surface topology characterized by a second surface roughness at a second depth within the substrate relative to the surface of the substrate. The first surface roughness may be greater than the second surface roughness, and the second depth may be greater than the first depth.

Abstract: Fabricating a photonic integrated circuit includes fabricating structures in one or more silicon layers. At least a first silicon layer comprises: one or more photonic structures, where the photonic structures include one or more waveguides and one or more photodetectors, and one or more light absorbing structures, where at least some of the light absorbing structures include doped silicon. Fabricating the photonic integrated circuit also includes fabricating at least one waveguide in the photonic integrated circuit for receiving light into at least one of the silicon layers.

Abstract: Fabricating a photonic integrated circuit includes fabricating structures in one or more silicon layers. At least a first silicon layer comprises: one or more photonic structures, where the photonic structures include one or more waveguides and one or more photodetectors, and one or more light absorbing structures, where at least some of the light absorbing structures include doped silicon. Fabricating the photonic integrated circuit also includes fabricating at least one waveguide in the photonic integrated circuit for receiving light into at least one of the silicon layers.

Abstract: A photodetector circuit is disclosed. The photodetector circuit includes an optical input configured to receive a source optical signal for detection by the photodetector circuit, an optical waveguide for coupling the optical input and at least one side of a plurality of sides of a photodiode, wherein the optical waveguide is configured to generate a first optical signal and a second optical signal from the source optical signal, and the photodiode coupled to the first optical waveguide, where the photodiode is illuminated on the at least one side by the first and second optical signals at different locations on the photodiode, where the photodiode generates a photocurrent based on the first and second optical signals reducing photocurrent saturation. Providing a delay between the first and second optical signals reduces an out-of-band frequency response of the photodiode circuit.

Abstract: A flip-chip manufacture is described. Methods of blocking adhesive underfill in flip-chip high speed component manufacture include creating topology discontinuities to prevent adhesive underfill material from interacting with RF sensitive regions on substrates.

Abstract: Systems and methods for non-hermetic Semiconductor Optical Amplifier (SOA) integration on a Silicon photonic (SiP) chip using Complementary Metal-Oxide-Semiconductor (CMOS) processes include creating a trench for placement of the SOA, wherein the trench is between two Spot Size Converters (SSCs) located on the SiP chip outside of the trench; forming pedestals in the trench in one or more existing CMOS layers of the SiP chip to guide vertical alignment of the SOA with the SSCs during its placement; and depositing metallic traces and a solder pattern in the trench above the pedestals to enable the SOAs to electrically bond and rest on the pedestals during reflow.

Abstract: Systems and methods for non-hermetic Semiconductor Optical Amplifier (SOA) integration on a Silicon photonic (SiP) chip using Complementary Metal-Oxide-Semiconductor (CMOS) processes include creating a trench for placement of the SOA, wherein the trench is between two Spot Size Converters (SSCs) located on the SiP chip outside of the trench; forming pedestals in the trench in one or more existing CMOS layers of the SiP chip to guide vertical alignment of the SOA with the SSCs during its placement; and depositing metallic traces and a solder pattern in the trench above the pedestals to enable the SOAs to electrically bond and rest on the pedestals during reflow.

Abstract: A photodetector circuit is disclosed. The photodetector circuit includes an optical input configured to receive a source optical signal for detection by the photodetector circuit, an optical waveguide for coupling the optical input and at least one side of a plurality of sides of a photodiode, wherein the optical waveguide is configured to generate a first optical signal and a second optical signal from the source optical signal, and the photodiode coupled to the first optical waveguide, where the photodiode is illuminated on the at least one side by the first and second optical signals at different locations on the photodiode, where the photodiode generates a photocurrent based on the first and second optical signals reducing photocurrent saturation. Providing a delay between the first and second optical signals reduces an out-of-band frequency response of the photodiode circuit.

Abstract: An integrated silicon-based photo-detection system, fabricated in an integrated silicon based structure on a silicon-on-insulator (SOI) wafer, includes a photodiode fabricated on an isolated area surrounded by a light barrier, where the light barrier is an area where the SOI wafer is removed, an optical waveguide that guides an input signal light into the photodiode, and external electrical traces that the free electron carriers flow into as photocurrent. A method of fabricating an integrated silicon-based photo-detection system in an integrated silicon based structure on a silicon-on-insulator (SOI) wafer, includes performing deep etching to create a light barrier surrounding an isolated area on the SOI wafer, fabricating a photodiode in the isolated area surrounded by the light barrier, fabricating an optical waveguide that guides an input signal light into the photodiode, and wirebonding external electrical traces to connect to the remainder of the integrated silicon based structure.