Patents by Inventor Francesc Guim Bernat

Francesc Guim Bernat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240407142
    Abstract: Hybrid and adaptive cooling systems are described. A method comprises selecting a cooling system type from a set of cooling system types of a hybrid cooling system to cool an electronic component of an electronic device, generating a control directive to activate a cooling component of the cooling system type, and performing thermal management of the electronic component of the electronic device using the cooling component of the cooling system type. Other embodiments are described and claimed.
    Type: Application
    Filed: August 9, 2024
    Publication date: December 5, 2024
    Applicant: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Uzair Qureshi, Marcos Carranza, Marek Piotrowski
  • Patent number: 12160368
    Abstract: Examples described herein relate to a device configured to allocate memory resources for packets received by the network interface based on received configuration settings. In some examples, the device is a network interface. Received configuration settings can include one or more of: latency, memory bandwidth, timing of when the content is expected to be accessed, or encryption parameters. In some examples, memory resources include one or more of: a cache, a volatile memory device, a storage device, or persistent memory. In some examples, based on a configuration settings not being available, the network interface is to perform one or more of: dropping a received packet, store the received packet in a buffer that does not meet the configuration settings, or indicate an error. In some examples, configuration settings are conditional where the settings are applied if one or more conditions is met.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Patrick Connor, Patrick G. Kutch, John J. Browne, Alexander Bachmutsky
  • Publication number: 20240396852
    Abstract: There is disclosed in one example an application-specific integrated circuit (ASIC), including: an artificial intelligence (AI) circuit; and circuitry to: identify a flow, the flow including traffic diverted from a core cloud service of a network to be serviced by an edge node closer to an edge of the network than to the core of the network; receive telemetry related to the flow, the telemetry including fine-grained and flow-level network monitoring data for the flow; operate the AI circuit to predict, from the telemetry, a future service-level demand for the edge node; and cause a service parameter of the edge node to be tuned according to the prediction.
    Type: Application
    Filed: August 1, 2024
    Publication date: November 28, 2024
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Mark A. Schmisseur, Timothy Verrall
  • Patent number: 12155539
    Abstract: Methods, systems, and use cases for orchestrator execution planning using a distributed ledger are discussed, including an orchestration system with memory and at least one processing circuitry coupled to the memory. The processing circuitry is configured to perform operations to generate an execution plan for a workload based on an SLA. The execution plan includes state transitions associated with corresponding edge service instances. A distributed ledger record is retrieved from the ledger based on a reinforcement learning reward value specified by the record. The reward value is associated with a state transition of the plurality of state transitions. An edge node is selected based on the retrieved distributed ledger record. Execution of an edge service instance of the plurality of edge service instances by the edge node is scheduled. The execution of the edge service instance corresponds to the state transition associated with the reinforcement learning reward value.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: November 26, 2024
    Assignee: Intel Corporation
    Inventors: Ned M. Smith, Kshitij Arun Doshi, Francesc Guim Bernat
  • Patent number: 12153722
    Abstract: Methods, apparatus, systems, and articles of manufacture to protect proprietary functionality and/or other content in hardware and software are disclosed. An example computer apparatus includes; a first circuit including a first interface, the first circuit associated with a first domain; a second circuit including a second interface, the second circuit associated with a second domain; and a chip manager to generate a first authenticated interface for the first interface using a first token and to generate a second authenticated interface for the second interface using a second token to enable communication between the first authenticated interface and the second authenticated interface.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: November 26, 2024
    Inventors: Sunil Cheruvu, Ria Cheruvu, Kshitij Doshi, Francesc Guim Bernat, Ned Smith, Anahit Tarkhanyan
  • Publication number: 20240385884
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to estimate workload complexity. An example apparatus includes processor circuitry to perform at least one of first, second, or third operations to instantiate payload interface circuitry to extract workload objective information and service level agreement (SLA) criteria corresponding to a workload, and acceleration circuitry to select a pre-processing model based on (a) the workload objective information and (b) feedback corresponding to workload performance metrics of at least one prior workload execution iteration, execute the pre-processing model to calculate a complexity metric corresponding to the workload, and select candidate resources based on the complexity metric.
    Type: Application
    Filed: December 23, 2021
    Publication date: November 21, 2024
    Inventors: Karthik Kumar, Timothy Verrall, Thomas Willhalm, Francesc Guim Bernat, Zhongyan Lu
  • Patent number: 12132661
    Abstract: In one embodiment, an apparatus includes: a monitor circuit to monitor traffic of a plurality of sources through the apparatus and maintain telemetry information regarding the traffic based at least in part on telemetry rules received from the plurality of sources, wherein the monitor circuit is to determine whether to send a callback message to a selected one of the plurality of sources, the callback message including telemetry information associated with the traffic of the selected source through the apparatus; and a storage coupled to the monitor circuit, the storage to store the telemetry information, wherein the monitor circuit is to access the telemetry information from the storage. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: October 29, 2024
    Assignee: Intel Corporation
    Inventor: Francesc Guim Bernat
  • Patent number: 12132825
    Abstract: Technologies for accelerated key caching in an edge hierarchy include multiple edge appliance devices organized in tiers. An edge appliance device receives a request for a key, such as a private key. The edge appliance device determines whether the key is included in a local key cache and, if not, requests the key from an edge appliance device included in an inner tier of the edge hierarchy. The edge appliance device may request the key from an edge appliance device included in a peer tier of the edge hierarchy. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys in the key cache for eviction. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys for pre-fetching. Those functions of the edge appliance device may be performed by an accelerator such as an FPGA. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: October 29, 2024
    Assignee: Intel Corporation
    Inventors: Timothy Verrall, Thomas Willhalm, Francesc Guim Bernat, Karthik Kumar, Ned M. Smith, Rajesh Poornachandran, Kapil Sood, Tarun Viswanathan, John J. Browne, Patrick Kutch
  • Patent number: 12130754
    Abstract: Examples described herein relate to a network device apparatus that includes a packet processing circuitry configured to determine if target data associated with a memory access request is stored in a different device than that identified in the memory access request and based on the target data associated with the memory access request identified as stored in a different device than that identified in the memory access request, cause transmission of the memory access request to the different device. In some examples, the memory access request comprises an identifier of a requester of the memory access request and the identifier comprises a Process Address Space identifier (PASID) and wherein the configuration that a redirection operation is permitted to be performed for a memory access request is based at least on the identifier.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: October 29, 2024
    Assignee: Intel Corporation
    Inventors: Karthik Kumar, Francesc Guim Bernat
  • Patent number: 12132790
    Abstract: An architecture to perform resource management among multiple network nodes and associated resources is disclosed. Example resource management techniques include those relating to: proactive reservation of edge computing resources; deadline-driven resource allocation; speculative edge QoS pre-allocation; and automatic QoS migration across edge computing nodes.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: October 29, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Patrick Bohan, Kshitij Arun Doshi, Brinda Ganesh, Andrew J. Herdrich, Monica Kenguva, Karthik Kumar, Patrick G Kutch, Felipe Pastor Beneyto, Rashmin Patel, Suraj Prabhakaran, Ned M. Smith, Petar Torre, Alexander Vul
  • Patent number: 12132805
    Abstract: Technologies for fulfilling service requests in an edge architecture include an edge gateway device to receive a request from an edge device or an intermediate tier device of an edge network to perform a function of a service by an entity hosting the service. The edge gateway device is to identify one or more input data to fulfill the request by the service and request the one or more input data from an edge resource identified to provide the input data. The edge gateway device is to provide the input data to the entity associated with the request.
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: October 29, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Petar Torre, Ned Smith, Brinda Ganesh, Evan Custodio, Suraj Prabhakaran
  • Patent number: 12132664
    Abstract: Example edge gateway circuitry to schedule service requests in a network computing system includes: gateway-level hardware queue manager circuitry to: parse the service requests based on service parameters in the service requests; and schedule the service requests in a queue based on the service parameters, the service requests received from client devices; and hardware queue manager communication interface circuitry to send ones of the service requests from the queue to rack-level hardware queue manager circuitry in a physical rack, the ones of the service requests corresponding to functions as a service provided by resources in the physical rack.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: October 29, 2024
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Suraj Prabhakaran, Ignacio Astilleros Diez, Timothy Verrall
  • Publication number: 20240353915
    Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to perform dynamic function control. An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to parse a packet for a function directive, activate a function associated with the function directive based on a type of the function directive being associated with an activation instruction, disable the function associated with the function directive based on the type of the function directive being associated with a deactivation instruction, and publish an active function list (AFL) and a passive function list (PFL) based on the type of the function directive.
    Type: Application
    Filed: July 3, 2024
    Publication date: October 24, 2024
    Inventors: Akhilesh S. Thyagaturu, Francesc Guim Bernat, Karthik Kumar, Stephen Thomas Palermo, John J. Browne
  • Patent number: 12126592
    Abstract: Systems and methods may be used to provide neutral host edge services in an edge network. An example method may include generating a virtual machine for a communication service provider at a compute device. The method may include receiving a user packet originated at a user device associated with the communication service provider and identifying dynamic route information related to the user packet using the virtual machine corresponding to the communication service provider. Data may be output corresponding to the user packet based on the dynamic route information.
    Type: Grant
    Filed: December 26, 2020
    Date of Patent: October 22, 2024
    Assignee: Intel Corporation
    Inventors: Kannan Babu Ramia, Deepak S, Palaniappan Ramanathan, Timothy Verrall, Francesc Guim Bernat
  • Patent number: 12127069
    Abstract: Methods, systems, and use cases for geofence-based edge service control and authentication are discussed, including an orchestration system with memory and at least one processing circuitry coupled to the memory. The processing circuitry is configured to perform operations to obtain, from a plurality of connectivity nodes providing edge services, physical location information, and resource availability information associated with each of the plurality of connectivity nodes. An edge-to-edge location graph (ELG) is generated based on the physical location information and the resource availability information, the ELG indicating a subset of the plurality of connectivity nodes that are available for executing a plurality of services associated with an edge workload. The connectivity nodes are provisioned with the ELG and a workflow execution plan to execute the plurality of services, the workflow execution plan including metadata with a geofence policy.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: October 22, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij Arun Doshi, Ned M. Smith, Ben McCahill, Miltiadis Filippou
  • Publication number: 20240348606
    Abstract: Various approaches for the verification of 5G networks, including the use of fingerprint-based IQ measurements for authentication and integrity monitoring, are discussed. In an example, a method of using fingerprints for authentication of network use includes: capturing in-phase and quadrature (IQ) data from a network connection between a user equipment (UE) and a 5G network; performing authentication of the network connection between the UE and the 5G network, by using a symbol of the IQ data as a random factor for the authentication; and monitoring the IQ data on an ongoing basis to verify the network connection between the UE and the 5G network. The method may also include creating a baseline IQ measurement from the IQ data when performing the authentication between the UE and the 5G network, and monitoring the IQ data by using a comparison of an ongoing IQ measurement to the baseline IQ measurement.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Inventors: Stephen T. Palermo, Valerie J. Parker, Patrick L. Connor, Francesc Guim Bernat, John Joseph Browne, Rajesh Poornachandran, Marcos E. Carranza
  • Patent number: 12120175
    Abstract: Technologies for providing selective offload of execution of an application to the edge include a device that includes circuitry to determine whether a section of an application to be executed by the device is available to be offloaded. Additionally, the circuitry is to determine one or more characteristics of an edge resource available to execute the section. Further, the circuitry is to determine, as a function of the one or more characteristics and a target performance objective associated with the section, whether to offload the section to the edge resource and offload, in response to a determination to offload the section, the section to the edge resource.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Ned Smith, Thomas Willhalm, Karthik Kumar, Timothy Verrall
  • Patent number: 12120595
    Abstract: Various approaches for the deployment and use of communication exclusion zones, defined for use with a satellite non-terrestrial network (including within a low-earth orbit satellite constellation), are discussed. In an example, defining and implementing a non-terrestrial communication exclusion zone includes: calculating based on a future orbital position of a low-earth orbit satellite vehicle, an exclusion condition for communications from the satellite vehicle; identifying, based on the exclusion condition and the future orbital position, a timing for implementing the exclusion condition for the communications from the satellite vehicle; and generating exclusion zone data for use by the satellite vehicle, the exclusion zone data indicating the timing for implementing the exclusion condition for the communications from the satellite vehicle.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Stephen T. Palermo, Chetan Hiremath, Rajesh Gadiyar, Jason K. Smith, Valerie J. Parker, Udayan Mukherjee, Neelam Chandwani, Francesc Guim Bernat, Ned M. Smith
  • Patent number: 12120012
    Abstract: A device of a service coordinating entity includes communications circuitry to communicate with a plurality of access networks via a corresponding plurality of network function virtualization (NFV) instances, processing circuitry, and a memory device. The processing circuitry is to perform operations to monitor stored performance metrics for the plurality of NFV instances. Each of the NFV instances is instantiated by a corresponding scheduler of a plurality of schedulers on a virtualization infrastructure of the service coordinating entity. A plurality of stored threshold metrics is retrieved, indicating a desired level for each of the plurality of performance metrics. A threshold condition is detected for at least one of the performance metrics for an NF V instance of the plurality of NFV instances, based on the retrieved plurality of threshold metrics. A hardware resource used by the NFV instance to communicate with an access network is adjusted based on the detected threshold condition.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: October 15, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Andrew J. Herdrich, Karthik Kumar, Felipe Pastor Beneyto, Edwin Verplanke, Rashmin Patel, Monica Kenguva, Brinda Ganesh, Alexander Vul, Ned M. Smith
  • Patent number: 12113853
    Abstract: Example methods, apparatus, and systems to manage quality of service with respect to service level agreements in a computing device are disclosed. An example apparatus includes a first mesh proxy assigned to a first platform-agnostic application, the first mesh proxy to generate a first resource request signal based on a first service level agreement requirement from the first platform-agnostic application; a second mesh proxy assigned to a second platform-agnostic application, the second mesh proxy to generate a second resource request signal based on a second service level agreement requirement from second platform-agnostic application; and a load balancer to allocate hardware resources for the first platform-agnostic application and the second platform-agnostic application based on the first resource request signal and the second resource request signal.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: October 8, 2024
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Andrew J. Herdrich, Kshitij Arun Doshi, Monica Kenguva, Ned M. Smith, Nilesh Jain, Brinda Ganesh, Rashmin Patel, Alexander Vul