Patents by Inventor Francesc Guim

Francesc Guim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250021482
    Abstract: Disclosed examples include accessing a memory access command, the memory access command identifying a memory address; determining a remote node that provides access to the memory address in a pooled memory shared by multiple nodes; and causing tunneling of the memory access command to the remote node to service the memory access command.
    Type: Application
    Filed: September 26, 2024
    Publication date: January 16, 2025
    Applicant: Intel Corporation
    Inventor: Francesc Guim Bernat
  • Patent number: 12197949
    Abstract: Technologies for providing attestation for function as a service flavors include a compute device including circuitry configured to obtain function definition data indicative of a set of operations to be performed in a function and a set of hardware resources to be utilized by the function, execute a benchmark operation to produce benchmark data indicative of a measured performance of the function, and sign the function definition data and the benchmark data to produce function flavor data. The circuitry is also configured to provide the function flavor data to one or more other compute devices for validation that the function, when executed on the hardware resources, provides the measured performance and write, to a distributed ledger, the function flavor data.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: January 14, 2025
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Kshitij Doshi, Ned M. Smith
  • Patent number: 12189545
    Abstract: In one embodiment, an apparatus includes: an interface to couple a plurality of devices of a system and enable communication according to a Compute Express Link (CXL) protocol. The interface may receive a consistent memory request having a type indicator to indicate a type of consistency to be applied to the consistent memory request. A request scheduler coupled to the interface may receive the consistent memory request and schedule it for execution according to the type of consistency, based at least in part on a priority of the consistent memory request and one or more pending consistent memory requests. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: January 7, 2025
    Assignee: Intel Corporation
    Inventors: Karthik Kumar, Francesc Guim Bernat
  • Patent number: 12189512
    Abstract: Examples described herein relate to an apparatus that includes a memory and at least one processor where the at least one processor is to receive configuration to gather performance data for a function from one or more platforms and during execution of the function, collect performance data for the function and store the performance data after termination of execution of the function. Some examples include an interface coupled to the at least one processor and the interface is to receive one or more of: an identifier of a function, resources to be tracked as part of function execution, list of devices to be tracked as part of function execution, type of monitoring of function execution, or meta-data to identify when the function is complete. Performance data can be accessed to determine performance of multiple executions of the short-lived function.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: January 7, 2025
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Steven Briscoe, Karthik Kumar, Alexander Bachmutsky, Timothy Verrall
  • Patent number: 12191987
    Abstract: Technologies for dynamically managing resources in disaggregated accelerators include an accelerator. The accelerator includes acceleration circuitry with multiple logic portions, each capable of executing a different workload. Additionally, the accelerator includes communication circuitry to receive a workload to be executed by a logic portion of the accelerator and a dynamic resource allocation logic unit to identify a resource utilization threshold associated with one or more shared resources of the accelerator to be used by a logic portion in the execution of the workload, limit, as a function of the resource utilization threshold, the utilization of the one or more shared resources by the logic portion as the logic portion executes the workload, and subsequently adjust the resource utilization threshold as the workload is executed. Other embodiments are also described and claimed.
    Type: Grant
    Filed: November 9, 2023
    Date of Patent: January 7, 2025
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Susanne M. Balle, Rahul Khanna, Sujoy Sen, Karthik Kumar
  • Publication number: 20250005457
    Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to provide recommendations for device management. An example non-transitory machine readable storage medium comprising instructions to cause programmable circuitry to at least: determine an action to be performed for a plurality of computing devices, the action includes information about the computing devices and an operation to be performed on the computing devices; compare the action with a plurality of prior actions; and report a predicted result based on a similarity of the action with at least one of the plurality of prior actions.
    Type: Application
    Filed: August 30, 2024
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Mario Jose Divan Koller, Mariano Ortega De Mues, Marcos Emanuel Carranza, Cesar Ignacio Martinez-Spessot, Mateo Guzman, Francesc Guim Bernat, John Joseph Browne, Mats Gustav Agerstam, Gavin Bartlett Lewis, Abhishek Pillai, Tejaswini Sirlapu
  • Patent number: 12182021
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to enable secure memory sharing in a multi-tenant edge network. Examples disclosed herein include mapping a first node to a memory region in response to receiving a memory access request from a second node mapped to the memory region, providing a private security key associated with the memory region to the first node, and applying a cache coherency protocol to the first node and the second node in response to the pooled memory controller mapping the first node to the memory region.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: December 31, 2024
    Assignee: Intel Corporation
    Inventor: Francesc Guim Bernat
  • Patent number: 12177099
    Abstract: Technologies for collecting metrics associated with a processing resource (e.g., central processing unit (CPU) resources, accelerator device resources, and the like) over a time window are disclosed. According to an embodiment presented herein, a network device receives, in an edge network, a request to provide one or more metrics associated with a processing resource, the request specifying a window indicative of a time period to capture the one or more metrics. The network device obtains the one or more metrics from the processing resource for the specified window and provides the obtained one or more metrics in response to the request.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: December 24, 2024
    Assignee: Intel Corporation
    Inventors: Raghu Kondapalli, Alexander Bachmutsky, Francesc Guim Bernat, Ned M. Smith, Trevor Cooper
  • Patent number: 12177131
    Abstract: A computing node includes a NIC and processing circuitry configured to select a subset of computing resources from a set of available computing resources to initiate a parameter sweep associated with a parameter sweep request received. A plurality of settings is applied to each computing resource of the subset to generate a plurality of resource mappings during the parameter sweep. Each resource mapping of the plurality of resource mappings indicates at least one computing resource of the subset and a corresponding at least one setting of the plurality of settings. Telemetry information for the subset of computing resources is retrieved, the telemetry information is generated during the parameter sweep. A resource mapping of the plurality of resource mappings is selected based on a comparison of the telemetry information with an SLO. A reconfiguration of the available computing resources is performed based on the selected resource mapping.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: December 24, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij Arun Doshi, Karol Weber, Marek Piotrowski, Piotr Wysocki
  • Patent number: 12175273
    Abstract: Embodiments described herein are generally directed to assigning virtual machine (VM) workloads to groupings/partitions of accelerator resources. In an example, a processing resource of a host system maintains: (i) a resource data structure containing resource utilization information for each of one or more accelerators associated with the host system; and (ii) a group data structure containing information regarding each group of multiple groups of one or more virtual functions (VFs) of the one or more accelerators that has been assigned for use by a respective VM of multiple VMs running on a virtual machine monitor (VMM) of the processing resource. A request to deploy a workload associated with a first VM is received. Responsive to the request, the workload is assigned to a VF of a group of the multiple groups determined to have resource capacity available to satisfy expected resource utilization of the workload.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: December 24, 2024
    Assignee: Intel Corporation
    Inventors: Devamekalai Nagasundaram, San Yen Wong, Haarika Madaka, Wei Seng Yeap, Marcos Carranza, Cesar Martinez Spessot, Francesc Guim Bernat, Rajesh Poornachandran
  • Patent number: 12166626
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for workload placement in an edge environment. An example apparatus for workload placement in an edge environment includes an orchestrator to receive a request to execute a workload from an edge platform within an edge environment, and a capability controller to analyze the request to determine operating parameters for the workload from the edge platform, and analyze candidate edge tier and edge platform placements based on the operating parameters, the orchestrator to determine a candidate edge tier and edge platform placement for the workload based on a candidate edge tier and edge platform placement that satisfies the operating parameters.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: December 10, 2024
    Assignee: INTEL CORPORATION
    Inventors: Kshitij Arun Doshi, Ned M. Smith, Francesc Guim Bernat
  • Patent number: 12164977
    Abstract: An apparatus comprising a network interface controller comprising a queue for messages for a thread executing on a host computing system, wherein the queue is dedicated to the thread; and circuitry to send a notification to the host computing system to resume execution of the thread when a monitoring rule for the queue has been triggered.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: December 10, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Patrick G. Kutch, Alexander Bachmutsky, Nicolae Octavian Popovici
  • Publication number: 20240407142
    Abstract: Hybrid and adaptive cooling systems are described. A method comprises selecting a cooling system type from a set of cooling system types of a hybrid cooling system to cool an electronic component of an electronic device, generating a control directive to activate a cooling component of the cooling system type, and performing thermal management of the electronic component of the electronic device using the cooling component of the cooling system type. Other embodiments are described and claimed.
    Type: Application
    Filed: August 9, 2024
    Publication date: December 5, 2024
    Applicant: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Uzair Qureshi, Marcos Carranza, Marek Piotrowski
  • Patent number: 12160368
    Abstract: Examples described herein relate to a device configured to allocate memory resources for packets received by the network interface based on received configuration settings. In some examples, the device is a network interface. Received configuration settings can include one or more of: latency, memory bandwidth, timing of when the content is expected to be accessed, or encryption parameters. In some examples, memory resources include one or more of: a cache, a volatile memory device, a storage device, or persistent memory. In some examples, based on a configuration settings not being available, the network interface is to perform one or more of: dropping a received packet, store the received packet in a buffer that does not meet the configuration settings, or indicate an error. In some examples, configuration settings are conditional where the settings are applied if one or more conditions is met.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: December 3, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Patrick Connor, Patrick G. Kutch, John J. Browne, Alexander Bachmutsky
  • Publication number: 20240396852
    Abstract: There is disclosed in one example an application-specific integrated circuit (ASIC), including: an artificial intelligence (AI) circuit; and circuitry to: identify a flow, the flow including traffic diverted from a core cloud service of a network to be serviced by an edge node closer to an edge of the network than to the core of the network; receive telemetry related to the flow, the telemetry including fine-grained and flow-level network monitoring data for the flow; operate the AI circuit to predict, from the telemetry, a future service-level demand for the edge node; and cause a service parameter of the edge node to be tuned according to the prediction.
    Type: Application
    Filed: August 1, 2024
    Publication date: November 28, 2024
    Applicant: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Mark A. Schmisseur, Timothy Verrall
  • Patent number: 12153722
    Abstract: Methods, apparatus, systems, and articles of manufacture to protect proprietary functionality and/or other content in hardware and software are disclosed. An example computer apparatus includes; a first circuit including a first interface, the first circuit associated with a first domain; a second circuit including a second interface, the second circuit associated with a second domain; and a chip manager to generate a first authenticated interface for the first interface using a first token and to generate a second authenticated interface for the second interface using a second token to enable communication between the first authenticated interface and the second authenticated interface.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: November 26, 2024
    Inventors: Sunil Cheruvu, Ria Cheruvu, Kshitij Doshi, Francesc Guim Bernat, Ned Smith, Anahit Tarkhanyan
  • Patent number: 12155539
    Abstract: Methods, systems, and use cases for orchestrator execution planning using a distributed ledger are discussed, including an orchestration system with memory and at least one processing circuitry coupled to the memory. The processing circuitry is configured to perform operations to generate an execution plan for a workload based on an SLA. The execution plan includes state transitions associated with corresponding edge service instances. A distributed ledger record is retrieved from the ledger based on a reinforcement learning reward value specified by the record. The reward value is associated with a state transition of the plurality of state transitions. An edge node is selected based on the retrieved distributed ledger record. Execution of an edge service instance of the plurality of edge service instances by the edge node is scheduled. The execution of the edge service instance corresponds to the state transition associated with the reinforcement learning reward value.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: November 26, 2024
    Assignee: Intel Corporation
    Inventors: Ned M. Smith, Kshitij Arun Doshi, Francesc Guim Bernat
  • Publication number: 20240385884
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to estimate workload complexity. An example apparatus includes processor circuitry to perform at least one of first, second, or third operations to instantiate payload interface circuitry to extract workload objective information and service level agreement (SLA) criteria corresponding to a workload, and acceleration circuitry to select a pre-processing model based on (a) the workload objective information and (b) feedback corresponding to workload performance metrics of at least one prior workload execution iteration, execute the pre-processing model to calculate a complexity metric corresponding to the workload, and select candidate resources based on the complexity metric.
    Type: Application
    Filed: December 23, 2021
    Publication date: November 21, 2024
    Inventors: Karthik Kumar, Timothy Verrall, Thomas Willhalm, Francesc Guim Bernat, Zhongyan Lu
  • Patent number: 12132661
    Abstract: In one embodiment, an apparatus includes: a monitor circuit to monitor traffic of a plurality of sources through the apparatus and maintain telemetry information regarding the traffic based at least in part on telemetry rules received from the plurality of sources, wherein the monitor circuit is to determine whether to send a callback message to a selected one of the plurality of sources, the callback message including telemetry information associated with the traffic of the selected source through the apparatus; and a storage coupled to the monitor circuit, the storage to store the telemetry information, wherein the monitor circuit is to access the telemetry information from the storage. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: October 29, 2024
    Assignee: Intel Corporation
    Inventor: Francesc Guim Bernat
  • Patent number: 12132790
    Abstract: An architecture to perform resource management among multiple network nodes and associated resources is disclosed. Example resource management techniques include those relating to: proactive reservation of edge computing resources; deadline-driven resource allocation; speculative edge QoS pre-allocation; and automatic QoS migration across edge computing nodes.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: October 29, 2024
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Patrick Bohan, Kshitij Arun Doshi, Brinda Ganesh, Andrew J. Herdrich, Monica Kenguva, Karthik Kumar, Patrick G Kutch, Felipe Pastor Beneyto, Rashmin Patel, Suraj Prabhakaran, Ned M. Smith, Petar Torre, Alexander Vul