Abstract: A chiller for cooling a beverage includes a reservoir configured to hold a heat exchange fluid and an evaporator coil arranged within the reservoir. The evaporator coil includes a plurality of windings configured to circulate a coolant, and projections extending from an exterior surface of one or more of the plurality of windings. The chiller further includes a chiller coil arranged in the reservoir, wherein the beverage is configured to flow through the chiller coil. When the coolant is circulated through the plurality of windings of the evaporator coil, a bank of frozen heat exchange fluid forms on the windings and on the projections.

Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.

Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.

Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.

Abstract: An approach is provided in which a multi-core processor's first core determines whether it controls a system frequency that drives a group of cores included in the multi-core processor. When the first core is not controlling the system frequency for the group of cores, the first core uses an internal voltage control module to provide control information to the first core's programmable voltage regulator and, in turn, independently control the first core's voltage level. When the first core is controlling the system frequency, the first core receives voltage control information from pervasive control to control the first core's voltage levels.

Abstract: Trick mode playback is implemented by disengaging a frame synchronization signal, and then decoding “I” and “P” frames to two (or more) buffers. Specifically, each buffer has a pointer that is associated with a memory/origin address. The pointers are locked in place by disengaging the frame synchronization signal. Once the pointers are locked in place, the “I” frames and “P” frames are decoded to the two buffers in an alternating fashion based on a continuous swapping of the memory addresses associated with the two pointers. Because both “I” and “P” frames (as opposed to only “I” frames) are decoded and displayed, the trick mode playback appears smoother. In addition, because the frame synchronization signal was disengaged, the frames can be decoded at a rate faster than a single frame time. That is, one frame need not be completely decoded and read out before the next frame is decoded.

Abstract: Loss of decoding time prior to the vertical synchronization signal when motion video is arbitrarily scaled and positioned by placing the frame switch point at the completion of frame decoding and synchronizing the bottom border of the scaled image therewith while maintaining low latency of decoded data. High latency operation is provided only when necessitated by minimal spill buffer capacity and in combination with fractional image size reduction in the decoding path in order to maintain image resolution without requiring additional memory.

Abstract: A digital video stream is digitally scaled to properly display on a device having a horizontal to vertical aspect ratio different than the source aspect ratio leaving a blank area on the device. Graphic data is digitally scaled separately to extend partially or completely into and therefore use the blank area. A compositing blender digitally combines the two prior to a display encoder which produces analog signals for driving the display device.

Abstract: A digital video decoder system, method and article of manufacture are provided having integrated scaling capabilities for presentation of video in full size or a predetermined reduced size, while at the same time allowing for reduced external memory requirements for frame buffer storage. The integrated system utilizes an existing decimation unit to scale the decoded stream of video data when the system is in scaled video mode. Display mode switch logic oversees switching between normal video mode and scaled video mode, wherein the switching occurs without perceptual degradation of a display of the decoded stream of video data. Scaled decoded video frames are buffered in a frame buffer which is partitioned depending upon whether the digital video decoding system is in normal video mode or scaled video mode. In scaled video mode, the frame buffer accommodates both full size I and P frames, as well as scaled I, P & B frames.

Abstract: Trick mode playback is implemented by disengaging a frame synchronization signal, and then decoding “I” and “P” frames to two (or more) buffers. Specifically, each buffer has a pointer that is associated with a memory/origin address. The pointers are locked in place by disengaging the frame synchronization signal. Once the pointers are locked in place, the “I” frames and “P” frames are decoded to the two buffers in an alternating fashion based on a continuous swapping of the memory addresses associated with the two pointers. Because both “I” and “P” frames (as opposed to only “I” frames) are decoded and displayed, the trick mode playback appears smoother. In addition, because the frame synchronization signal was disengaged, the frames can be decoded at a rate faster than a single frame time. That is, one frame need not be completely decoded and read out before the next frame is decoded.

Abstract: A digital video stream is digitally scaled to properly display on a device having a horizontal to vertical aspect ratio different than the source aspect ratio leaving a blank area on the device. Graphic data is digitally scaled separately to extend partially or completely into and therefore use the blank area. A compositing blender digitally combines the two prior to a display encoder which produces analog signals for driving the display device.

Abstract: Loss of decoding time prior to the vertical synchronization signal when motion video is arbitrarily scaled and positioned by placing the frame switch point at the completion of frame decoding and synchronizing the bottom border of the scaled image therewith while maintaining low latency of decoded data. High latency operation is provided only when necessitated by minimal spill buffer capacity and in combination with fractional image size reduction in the decoding path in order to maintain image resolution without requiring additional memory.

Abstract: A digital video decoder system, method and article of manufacture are provided having integrated scaling capabilities for presentation of video in full size or a predetermined reduced size, while at the same time allowing for reduced external memory requirements for frame buffer storage. The integrated system utilizes an existing decimation unit to scale the decoded stream of video data when the system is in scaled video mode. Display mode switch logic oversees switching between normal video mode and scaled video mode, wherein the switching occurs without perceptual degradation of a display of the decoded stream of video data. Scaled decoded video frames are buffered in a frame buffer which is partitioned depending upon whether the digital video decoding system is in normal video mode or scaled video mode. In scaled video mode, the frame buffer accommodates both full size I and P frames, as well as scaled I, P & B frames.

Abstract: A digital video decoder system, method and article of manufacture are provided having integrated scaling capabilities for presentation of video in full size or a predetermined reduced size, while at the same time allowing for reduced external memory requirements for frame buffer storage. The integrated system utilizes an existing decimation unit to scale the decoded stream of video data when the system is in scaled video mode. Display mode switch logic oversees switching between normal video mode and scaled video mode, wherein the switching occurs without perceptual degradation of a display of the decoded stream of video data. Scaled decoded video frames are buffered in a frame buffer which is partitioned depending upon whether the digital video decoding system is in normal video mode or scaled video mode. In scaled video mode, the frame buffer accommodates both full size I and P frames, as well as scaled I, P & B frames.