Abstract: A transmitter including a frequency synthesizer with a voltage-controlled oscillator that provides an oscillating signal, a programmable delay circuit that delays the oscillating signal to provide a delayed oscillating signal, a power amplifier that is configured to amplify the delayed oscillating signal for transmission sufficient to produce interference, and a delay controller that programs the delay circuit with a delay time that reduces interference caused by coupling from the power amplifier to the voltage-controlled oscillator. The delay circuit may be programmed to reduce control voltage change of the voltage-controlled oscillator as a function of delay change, and/or to reduce phase noise degradation at an output of the transmitter as a function of delay change. The delay may be adjusted based on detected operating temperature. A calibration value may be determined at a calibration frequency, in which a frequency offset may be determined based on a selected channel frequency.

Abstract: A switching power amplifier with harmonic suppression including a polyphase converter and a power amplifier stage. The polyphase converter converts a frequency or phase modulated input signal into a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when high, and a negative 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when low. The power amplifier stage includes first and second branches coupled between upper and lower nodes, each including series-coupled P-channel and N-channel transistors forming an intermediate output node. The transistors of the first branch are controlled by the 50% duty cycle signal, and the transistors of the second branch are controlled by the positive and negative 25% duty cycle signals. The first and second branches generate output currents that are superimposed with each other to suppress third and fifth harmonics.

Abstract: A transmitter including a frequency synthesizer with a voltage-controlled oscillator that provides an oscillating signal, a programmable delay circuit that delays the oscillating signal to provide a delayed oscillating signal, a power amplifier that is configured to use the delayed oscillating signal for transmitting a signal, and a delay controller that programs the delay circuit with a delay time that reduces interference caused by coupling from the power amplifier to the voltage-controlled oscillator. The delay circuit may be programmed to reduce control voltage change of the voltage-controlled oscillator as a function of delay change, and/or to reduce phase noise degradation at an output of the transmitter as a function of delay change. The delay may be adjusted based on detected operating temperature. A calibration value may be determined at a calibration frequency, in which a frequency offset may be determined based on a selected channel frequency.

Abstract: A phase-locked loop (PLL) that provides a local oscillator signal for a radio. An oscillator of the PLL supplies an oscillator output signal. Control logic receives a request to change the oscillator output signal to a new frequency and responds to the request by setting a first capacitor circuit of the oscillator to a first capacitance that corresponds to a predetermined frequency of the oscillator output signal. The control logic also responds to the request by setting one or more other capacitor circuits of the oscillator according to temperature and according to a frequency difference between the predetermined frequency and the new frequency. After responding to the request by setting the first capacitor circuit and the one or more other capacitor circuits, the PLL locks to the new frequency using a signal from the PLL loop filter to adjust another capacitor circuit in the oscillator.

Abstract: A phase-locked loop (PLL) that provides a local oscillator signal for a radio. An oscillator of the PLL supplies an oscillator output signal. Control logic receives a request to change the oscillator output signal to a new frequency and responds to the request by setting a first capacitor circuit of the oscillator to a first capacitance that corresponds to a predetermined frequency of the oscillator output signal. The control logic also responds to the request by setting one or more other capacitor circuits of the oscillator according to temperature and according to a frequency difference between the predetermined frequency and the new frequency. After responding to the request by setting the first capacitor circuit and the one or more other capacitor circuits, the PLL locks to the new frequency using a signal from the PLL loop filter to adjust another capacitor circuit in the oscillator.

Abstract: A first three state driver injects a first clock signal into a crystal through an input node during a startup phase of a crystal oscillator and a second three state driver injects a second signal into the crystal through an output node during the startup phase. The first and second signals are anti-phase signals. The crystal oscillator circuit includes a first amplifier that is used during starting up and steady-state operation and includes a second amplifier. The injection through the input and output nodes is disabled after a fixed time. After injection ends, the second amplifier is turned on if voltage on the output node has reached a desired voltage and left off otherwise. If the second amplifier is turned on, the second amplifier is turned off when the voltage on the output node reaches the desired voltage.

Abstract: A switching power amplifier with harmonic suppression including a polyphase converter and a power amplifier stage. The polyphase converter converts a frequency or phase modulated input signal into a 50% duty cycle rail-to-rail signal, a positive 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when high, and a negative 25% duty cycle rail-to-rail signal that is centered with the 50% duty cycle signal when low. The power amplifier stage includes first and second branches coupled between upper and lower nodes, each including series-coupled P-channel and N-channel transistors forming an intermediate output node. The transistors of the first branch are controlled by the 50% duty cycle signal, and the transistors of the second branch are controlled by the positive and negative 25% duty cycle signals. The first and second branches generate output currents that are superimposed with each other to suppress third and fifth harmonics.

Abstract: A wireless transceiver circuit with an impedance matching network within an integrated circuit is disclosed. In some embodiments, the impedance matching network utilizes an inductor, having two portions, disposed on two different metal layers of the integrated circuit. The first end of the first portion of the inductor is in communication with an antenna. The second end of the second portion is in communication with a low noise amplifier for receiving signals and a power amplifier for transmitting RF signals. The second end of the first portion is connected to the first end of the second portion using a via. In another embodiment, the two portions are disposed on the same metal layer, wherein one portion is disposed within the other with a gap separating the two portions. These configurations require less space than using two separate inductors and also have a low coupling coefficient.

Abstract: A wireless transceiver circuit with an impedance matching network within an integrated circuit is disclosed. In some embodiments, the impedance matching network utilizes an inductor, having two portions, disposed on two different metal layers of the integrated circuit. The first end of the first portion of the inductor is in communication with an antenna. The second end of the second portion is in communication with a low noise amplifier for receiving signals and a power amplifier for transmitting RF signals. The second end of the first portion is connected to the first end of the second portion using a via. In another embodiment, the two portions are disposed on the same metal layer, wherein one portion is disposed within the other with a gap separating the two portions. These configurations require less space than using two separate inductors and also have a low coupling coefficient.

Abstract: A system and method for accurately determining a distance between two network devices using a Channel Sounding application is disclosed. The network devices each guarantee a fixed phase relationship between the transmit circuit and the receive circuit. In one embodiment, this is achieved by incorporating the divider within the phase locked loop. The divider may have a reset, such that it can be initialized to a predetermined state. Further, by utilizing a divider disposed within the phase locked loop with a reset, the quadrature signal generator is guaranteed to output clocks for the transmit circuit and the receive circuit that have a constant phase relationship.

Abstract: Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. For disclosed embodiments, a filter circuit is coupled between a first internal node and a connection pad for an integrated circuit. The filter circuit includes a first inductance, a variable capacitance, and a second inductance. The capacitance amount for the variable capacitance is controlled to tune filtering for the filter circuit to a harmonic of a frequency for a transmit output signal. A power amplifier outputs the transmit output signal to the connection pad without passing through the filter circuit. The filter circuit filters the harmonic of the frequency for the transmit output signal, shunting harmonic current to ground. For one embodiment, the filtered harmonic is a third harmonic of the transmit frequency. For one embodiment, the transmit output signal has an output power greater than or equal to 15 dBm.

Abstract: A transmitter including a frequency synthesizer with a voltage-controlled oscillator that provides an oscillating signal, a programmable delay circuit that delays the oscillating signal to provide a delayed oscillating signal, a power amplifier that is configured to use the delayed oscillating signal for transmitting a signal, and a delay controller that programs the delay circuit with a delay time that reduces interference caused by coupling from the power amplifier to the voltage-controlled oscillator. The delay circuit may be programmed to reduce control voltage change of the voltage-controlled oscillator as a function of delay change, and/or to reduce phase noise degradation at an output of the transmitter as a function of delay change. The delay may be adjusted based on detected operating temperature. A calibration value may be determined at a calibration frequency, in which a frequency offset may be determined based on a selected channel frequency.

Abstract: Systems and methods are disclosed for on-chip harmonic filtering for radio frequency (RF) communications. For disclosed embodiments, a filter circuit is coupled between a first internal node and a connection pad for an integrated circuit. The filter circuit includes a first inductance, a variable capacitance, and a second inductance. The capacitance amount for the variable capacitance is controlled to tune filtering for the filter circuit to a harmonic of a frequency for a transmit output signal. A power amplifier outputs the transmit output signal to the connection pad without passing through the filter circuit. The filter circuit filters the harmonic of the frequency for the transmit output signal, shunting harmonic current to ground. For one embodiment, the filtered harmonic is a third harmonic of the transmit frequency. For one embodiment, the transmit output signal has an output power greater than or equal to 15 dBm.

Abstract: In an embodiment, an apparatus includes: a transmit circuit to upconvert a baseband signal to a first differential radio frequency (RF) signal, the transmit circuit to convert the first differential RF signal to a first single-ended RF signal; a duty cycle correction circuit coupled to the transmit circuit to receive the first single-ended RF signal and compensate for a duty cycle variation in the first single-ended RF signal to output a duty cycle-corrected RF signal; a conversion circuit to convert the duty cycle-corrected RF signal to a second differential RF signal; and an interface circuit to transfer the second differential RF signal from a first ground domain to a second ground domain.

Abstract: An apparatus includes a signal generator. The signal generator includes a voltage controlled oscillator (VCO) coupled to provide an output signal having a frequency. The signal generator further includes an asymmetric divider coupled to receive the output signal of the VCO and to provide an output signal. The output signal of the asymmetric divider has a frequency that is half the frequency of the output signal of the VCO. The asymmetric divider presents a balanced load to the VCO.

Abstract: An apparatus includes a signal generator. The signal generator includes a voltage controlled oscillator (VCO) coupled to provide an output signal having a frequency. The signal generator further includes an asymmetric divider coupled to receive the output signal of the VCO and to provide an output signal. The output signal of the asymmetric divider has a frequency that is half the frequency of the output signal of the VCO. The asymmetric divider presents a balanced load to the VCO.

Abstract: Programmable divider circuitry is disclosed that utilizes two cascaded divider cells to generate division ratios from 4 to 7 and utilizes an output signal from one of the divider cells to sample and synchronize the divider output signal. The operation of the programmable divider circuitry improves the consistency of duty cycles generated across the different division ratios. Further techniques are also applied to make more consistent the duty cycles depending upon the division ratio selected.

Abstract: A voltage controlled oscillator-phase lock loop (VCO-PLL) system includes a voltage controlled oscillator (VCO) system implementing four-channel architecture, such that two bands support two channels; a phase-locked-loop (PLL) system; and a mixer system. The VCO system further includes a control circuit; a first cross-coupled oscillator system adapted to receive a source voltage; a second cross-coupled oscillator system adapted to receive the source voltage; and a plurality of isolation buffer systems adapted to protect the first and second cross-coupled oscillator systems.

Abstract: A voltage controlled oscillator-phase lock loop (VCO-PLL) system includes a voltage controlled oscillator (VCO) system implementing four-channel architecture, such that two bands support two channels; a phase-locked-loop (PLL) system; and a mixer system. The VCO system further includes a control circuit; a first cross-coupled oscillator system adapted to receive a source voltage; a second cross-coupled oscillator system adapted to receive the source voltage; and a plurality of isolation buffer systems adapted to protect the first and second cross-coupled oscillator systems.