Abstract: A system securely buffers hard disk drive data using a host side eXlusive OR (XOR) encryption engine. A host communicates with an encryption interface interposed between the host and a client. Communicatively coupled to the encryption interface is an external buffer for the collection and processing of data. A host side XOR encryption engine, using a random seed, encrypts data originating from the host and places it on the external buffer. Once collected at the buffer and ready for transmittal to the client, the encrypted data is retrieved by the encryption interface and decrypted using the same random seed. The clear data is then encrypted once again using a robust encryption means such as Advance Encryption Standard (AES) encryption by a client side device for conveyance to the client.

Abstract: A system securely buffers hard disk drive data using a host side eXlusive OR (XOR) encryption engine. A host communicates with an encryption interface interposed between the host and a client. Communicatively coupled to the encryption interface is an external buffer for the collection and processing of data. A host side XOR encryption engine, using a random seed, encrypts data originating from the host and places it on the external buffer. Once collected at the buffer and ready for transmittal to the client, the encrypted data is retrieved by the encryption interface and decrypted using the same random seed. The clear data is then encrypted once again using a robust encryption means such as Advance Encryption Standard (AES) encryption by a client side device for conveyance to the client.

Abstract: A hard disk drive chip set includes an analog chip including all of the analog functions for the hard disk drive except for a motor controller, and a digital chip including all of the digital functions for the hard disk drive including a plurality of read channels. The analog chip is implemented in a BiCMOS process and includes read path amplification, reference and bias circuitry, thermal asperity control and magneto resistivity asymmetry compensation circuitry. The digital chip is implemented in a CMOS process and includes an analog-to-digital converter, a servo processor circuit, and a hard disk controller. Each of the read channels include an FIR filter, an ITR circuit, and a Viterbi detector. A hard disk drive using the chip set includes the analog chip on a first circuit board, and the digital chip, an external memory, and a motor controller on a second circuit board.

Abstract: A partial response Class 4 detector in a recording and retrieval system and method of operating the detector for correcting the timing error of the detector. The detector includes a sequence table and comparison circuitry for comparing a sequence of data samples that includes previous and subsequent data samples with allowed sequences determined from the sequence table. When the sequence is an allowed sequence then there is high likelihood that data sample is correct, and the timing error for the data sample is determined in the phase error estimator and is corrected for. Otherwise, no correction is made for the timing error. In the preferred embodiment of the invention the coordinates of the sequence table correspond to the data samples, and the slope of the data stream at the data sample is stored in the sequence table. This reduces the size and increases the speed of the phase error estimator since the slope is now provided to it from the sequence table and it does not need determine the slope.

Abstract: A Hilbert transform is used to process perpendicular magnetic recording signals from both single layer and dual layer disks to produce a complex analytic signal. This complex analytic signal is used to derive angles of magnetization, which depend on the distance between recorded magnetic transitions and consequently which can be used in error estimation. Moreover, the Hilbert transform in cooperation with an equalizer FIR optimizes transformation of the signal such that conventional longitudinal recording processing methods can subsequently be used to process the signal that is read back from the magnetic recording medium.

Abstract: A partial response Class 4 detector in a recording and retrieval system and method of operating the detector for correcting the timing error of the detector. The detector includes a sequence table and comparison circuitry for comparing a sequence of data samples that includes previous and subsequent data samples with allowed sequences determined from the sequence table. When the sequence is an allowed sequence then there is high likelihood that data sample is correct, and the timing error for the data sample is determined in the phase error estimator and is corrected for. Otherwise, no correction is made for the timing error. In the preferred embodiment of the invention the coordinates of the sequence table correspond to the data samples, and the slope of the data stream at the data sample is stored in the sequence table. This reduces the size and increases the speed of the phase error estimator since the slope is now provided to it from the sequence table and it does not need determine the slope.

Abstract: A Hilbert transform is used to process perpendicular magnetic recording signals from both single layer and dual layer disks to produce a complex analytic signal. This complex analytic signal is used to derive angles of magnetization, which depend on the distance between recorded magnetic transitions and consequently which can be used in error estimation. Moreover, the Hilbert transform in cooperation with an equalizer FIR optimizes transformation of the signal such that conventional longitudinal recording processing methods can subsequently be used to process the signal that is read back from the magnetic recording medium.

Abstract: A partial response Class 4 detector in a recording and retrieval system and method of operating the detector for correcting the timing error of the detector. The detector includes a sequence table and comparison circuitry for comparing a sequence of data samples that includes previous and subsequent data samples with allowed sequences determined from the sequence table. When the sequence is an allowed sequence then there is high likelihood that data sample is correct, and the timing error for the data sample is determined in the phase error estimator and is corrected for. Otherwise, no correction is made for the timing error. In the preferred embodiment of the invention the coordinates of the sequence table correspond to the data samples, and the slope of the data stream at the data sample is stored in the sequence table. This reduces the size and increases the speed of the phase error estimator since the slope is now provided to it from the sequence table and it does not need determine the slope.

Abstract: A partial response Class 4 detector in a recording and retrieval system and method of operating the detector for correcting the timing error of the detector. The detector includes a sequence table and comparison circuitry for comparing a sequence of data samples that includes previous and subsequent data samples with allowed sequences determined from the sequence table. When the sequence is an allowed sequence then there is high likelihood that data sample is correct, and the timing error for the data sample is determined in the phase error estimator and is corrected for. Otherwise, no correction is made for the timing error. In the preferred embodiment of the invention the coordinates of the sequence table correspond to the data samples, and the slope of the data stream at the data sample is stored in the sequence table. This reduces the size and increases the speed of the phase error estimator since the slope is now provided to it from the sequence table and it does not need determine the slope.

Abstract: An elementary cell structure for programmable time-continuous analog filters and in particular for the processing of analog signals in read/write operations on magnetic supports comprises an amplifier stage provided with a pair of structurally identical transconductance half-cells connected together in a common circuit node. With a cascade of cells of this type is provided a time-continuous analog delay line which is used in a transverse time-continuous analog filter. This filter comprises a cascade of identical delay lines connected through multiplier nodes to a final summation node.

Abstract: A partial response Class 4 detector in a recording and retrieval system and method of operating the detector for correcting the timing error of the detector. The detector includes a sequence table and comparison circuitry for comparing a sequence of data samples that includes previous and subsequent data samples with allowed sequences determined from the sequence table. When the sequence is an allowed sequence then there is high likelihood that data sample is correct, and the timing error for the data sample is determined in the phase error estimator and is corrected for. Otherwise, no correction is made for the timing error. In the preferred embodiment of the invention the coordinates of the sequence table correspond to the data samples, and the slope of the data stream at the data sample is stored in the sequence table. This reduces the size and increases the speed of the phase error estimator since the slope is now provided to it from the sequence table and it does not need determine the slope.

Abstract: Parallel processing in the form of two PR4 Viterbi Detectors connected in parallel operates to increase the maximum channel speed of a given data channel of a magnetic media. According to a target equation defined as Read(D)=(1−D2)2Written(D), in which D is the delay of a data of the channel, a first Viterbi Detector processes even data samples of the channel that have been equalized according to the target equation and a second Viterbi Detector connected in parallel processes odd data samples of the channel that have likewise been equalized according to the target equation. The use of two parallel-connected Viterbi Detectors in this fashion allows data to be processed at half-rate rather than full-rate, thereby increasing the overall channel speed.

Abstract: The invention relates to a basic cell for comparing a first and a second digital signal, of the type having at least a first and a second input and a first and a second output and comprising at least one logic gate receiving digital signals at a first and a second signal input, and which comprises at least a first and a second controlled switch inserted in parallel with each other between the output terminal of the logic gate and the second output from the cell, the first switch being also connected between the first input and the first output of the cell and the second switch being also connected between the second input and the second output of the cell. The invention also relates to a digital comparator comprising a plurality of basic cells according to the invention.

Abstract: A high-pass filter in particular for high-frequency applications and of the type comprising at least one input terminal (IN) and at least one output terminal (OUT) between which is defined a transfer function (FdT) and is inserted a biquadratic cell (18) incorporating a series of transconductance stages (2, 3, 4, 5) comprises a generator circuit (29) of variable currents (i.sub.K1, i.sub.K2) connected between a pair of stages (2, 3) of the biquadratic cell (18) and a voltage reference (GND). Said generator allows introduction of programmable zeroes in the transfer function (FdT) of the filter (20).