Patents by Inventor Francesco Caggioni

Francesco Caggioni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10455501
    Abstract: System and method of frame alignment at a receiver with power optimization mechanisms. A framer at the receiver is configured to process data streams from multiple physical lanes and/or multiple channels serially. The receiver may include multiple framers that process different sets of data streams in parallel. A framer may enter a power reduction mode after all the channels associated therewith have achieved frame alignment. The framer can be restarted to perform frame alignment processes on a particular channel responsive to an indication that the channel transitions to an out-of-frame state. The “out-of-frame” indication may be generated by a forward error correction (FEC) decoder when it detects an excessive number of uncorrectable errors in the channel.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 22, 2019
    Assignee: MACOM Connectivity Solutions, LLC
    Inventors: Francesco Caggioni, Dimitrios Giannakopoulos
  • Patent number: 10313102
    Abstract: System and method of frame alignment at a receiver with power optimization mechanisms. A framer is configured to perform a frame alignment process on a data stream and enter an inactive state after frame alignment is achieved. In the inactive state, the circuits used to perform the frame alignment process in the framer can be powered down or otherwise placed in a power reduction mode. Responsive to an indication that data processing at the receiver becomes “out-of-frame” again, the framer can wake up from the inactive state and restart the frame alignment process. An “out-of-frame” indication may be generated by error detection logic (e.g., forward error correction (FEC) decoder) when it detects an excessive number of uncorrectable errors.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 4, 2019
    Assignee: MACOM Connectivity Solutions, LLC
    Inventors: Francesco Caggioni, Dimitrios Giannakopoulos
  • Patent number: 10142091
    Abstract: System and method of frame alignment at a receiver with power optimization mechanisms. A framer uses one or more comparators to search for the FAW in the incoming data, with each comparator configured to serially compare multiple windows of a parallel M-bit block (as provided from a parallel data bus) with the FAW. Multiple comparators in the framer may operate in parallel to search for the FAW at different windows. This configuration can significantly reduce the comparator count and so the gate count as well as the chip area in a framer. Power consumption can be advantageously reduced as one comparator operating serially consumes less power than multiple comparators in parallel because less gate toggling is involved.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: November 27, 2018
    Assignee: MACOM CONNECTIVITY SOLUTIONS, LLC
    Inventors: Francesco Caggioni, Dimitrios Giannakopoulos
  • Publication number: 20180183564
    Abstract: System and method of frame alignment at a receiver with power optimization mechanisms. A framer is configured to perform a frame alignment process on a data stream and enter an inactive state after frame alignment is achieved. In the inactive state, the circuits used to perform the frame alignment process in the framer can be powered down or otherwise placed in a power reduction mode. Responsive to an indication that data processing at the receiver becomes “out-of-frame” again, the framer can wake up from the inactive state and restart the frame alignment process. An “out-of-frame” indication may be generated by error detection logic (e.g., forward error correction (FEC) decoder) when it detects an excessive number of uncorrectable errors.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Inventors: Francesco CAGGIONI, Dimitrios GIANNAKOPOULOS
  • Publication number: 20180183565
    Abstract: System and method of frame alignment at a receiver with power optimization mechanisms. A framer uses one or more comparators to search for the FAW in the incoming data, with each comparator configured to serially compare multiple windows of a parallel M-bit block (as provided from a parallel data bus) with the FAW. Multiple comparators in the framer may operate in parallel to search for the FAW at different windows. This configuration can significantly reduce the comparator count and so the gate count as well as the chip area in a framer. Power consumption can be advantageously reduced as one comparator operating serially consumes less power than multiple comparators in parallel because less gate toggling is involved.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Inventors: Francesco CAGGIONI, Dimitrios GIANNAKOPOULOS
  • Publication number: 20180184373
    Abstract: System and method of frame alignment at a receiver with power optimization mechanisms. A framer at the receiver is configured to process data streams from multiple physical lanes and/or multiple channels serially. The receiver may include multiple framers that process different sets of data streams in parallel. A framer may enter a power reduction mode after all the channels associated therewith have achieved frame alignment. The framer can be restarted to perform frame alignment processes on a particular channel responsive to an indication that the channel transitions to an out-of-frame state. The “out-of-frame” indication may be generated by a forward error correction (FEC) decoder when it detects an excessive number of uncorrectable errors in the channel.
    Type: Application
    Filed: December 22, 2016
    Publication date: June 28, 2018
    Inventors: Francesco CAGGIONI, Dimitrios GIANNAKOPOULOS
  • Patent number: 9590756
    Abstract: Various aspects provide for mapping a plurality of signals to generate a combined signal. An aggregation component is configured for generating a combined signal that comprises a higher data rate than a data rate associated with a plurality of signals based on mapped data associated with the plurality of signals. The aggregation component comprises a mapper component. The mapper component is configured for generating the mapped data based on a mapping distribution pattern associated with a generic mapping procedure. In an aspect, a de-aggregation component is configured for recovering the plurality of signals from a pseudo signal transmitted at a data rate of the combined signal. In another aspect, the de-aggregation component comprises a de-mapper component configured for de-mapping the mapped data based on the mapping distribution pattern associated with the generic mapping procedure.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: March 7, 2017
    Assignee: APPLIED MICRO CIRCUITS CORPORATION
    Inventors: Francesco Caggioni, Dimitrios Giannakopoulos
  • Patent number: 9337959
    Abstract: Systems and methods for detecting defect propagation in a networked environment comprising a defect detection component to detect defects in an aggregate signal and/or in individual signals; and a replacement signal component to generate a maintenance signal to replace defective signals detected by the defect detection component. The maintenance signal can be a uniform signal type regardless of a type associated with a defective signal. The maintenance signal can replace a defective signal during aggregation, by an aggregation component.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: May 10, 2016
    Assignee: APPLIED MICRO CIRCUITS CORPORATION
    Inventors: Francesco Caggioni, Dimitrios Giannakopoulos
  • Patent number: 9246617
    Abstract: Various aspects provide for aggregating a plurality of signals to generate a combined signal. An aggregation component is configured for reformatting a plurality of first signals and combining the plurality of first signals to generate a combined signal that comprises a higher data rate than a data rate associated with the plurality of first signals. A transmitter component is configured for receiving the combined signal and generating one or more data streams based on the combined signal. In an aspect, the aggregation component is additionally configured for reformatting and/or combining the plurality of first signals and at least one second signal to generate the combined signal. In another aspect, a receiver component is configured for generating a pseudo signal at a data rate of the combined signal. In yet another aspect, a de-aggregation component is configured for recovering the plurality of first signals and/or the at least one second signal from the pseudo signal.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: January 26, 2016
    Assignee: Applied Micro Circuits Corporation
    Inventors: Francesco Caggioni, Dimitrios Giannakopoulos
  • Patent number: 9088403
    Abstract: Various aspects provide for modifying a data stream for rate adaptation. A clock component receives a data stream at a first clock rate. In an aspect, a rate adaptation component inserts a first identification codeword into a particular location in the data stream based on a set of encoding rules in response to a determination that the first clock rate is lower than a second clock rate associated with a device configured for receiving a rate-adapted version of the data stream. In another aspect, the rate adaptation component removes a predefined codeword from the data stream and transforms another predefined codeword in the data stream into a second identification codeword in response to a determination that the first clock rate is greater than the second clock rate.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: July 21, 2015
    Assignee: Applied Micro Circuts Corporation
    Inventors: Francesco Caggioni, Dimitrios Giannakopoulos
  • Publication number: 20150106679
    Abstract: Systems and methods for detecting defect propagation in a networked environment comprising a defect detection component to detect defects in an aggregate signal and/or in individual signals; and a replacement signal component to generate a maintenance signal to replace defective signals detected by the defect detection component. The maintenance signal can be a uniform signal type regardless of a type associated with a defective signal. The maintenance signal can replace a defective signal during aggregation, by an aggregation component.
    Type: Application
    Filed: October 14, 2013
    Publication date: April 16, 2015
    Applicant: APPLIED MICRO CIRCUITS CORPORATION
    Inventors: Francesco Caggioni, Dimitrios Giannakopoulos
  • Publication number: 20150078406
    Abstract: Various aspects provide for mapping a plurality of signals to generate a combined signal. An aggregation component is configured for generating a combined signal that comprises a higher data rate than a data rate associated with a plurality of signals based on mapped data associated with the plurality of signals. The aggregation component comprises a mapper component. The mapper component is configured for generating the mapped data based on a mapping distribution pattern associated with a generic mapping procedure. In an aspect, a de-aggregation component is configured for recovering the plurality of signals from a pseudo signal transmitted at a data rate of the combined signal. In another aspect, the de-aggregation component comprises a de-mapper component configured for de-mapping the mapped data based on the mapping distribution pattern associated with the generic mapping procedure.
    Type: Application
    Filed: September 16, 2013
    Publication date: March 19, 2015
    Applicant: APPLIED MICRO CIRCUITS CORPORATION
    Inventors: Francesco Caggioni, Dimitrios Giannakopoulos
  • Publication number: 20150071311
    Abstract: Various aspects provide for aggregating a plurality of signals to generate a combined signal. An aggregation component is configured for reformatting a plurality of first signals and combining the plurality of first signals to generate a combined signal that comprises a higher data rate than a data rate associated with the plurality of first signals. A transmitter component is configured for receiving the combined signal and generating one or more data streams based on the combined signal. In an aspect, the aggregation component is additionally configured for reformatting and/or combining the plurality of first signals and at least one second signal to generate the combined signal. In another aspect, a receiver component is configured for generating a pseudo signal at a data rate of the combined signal. In yet another aspect, a de-aggregation component is configured for recovering the plurality of first signals and/or the at least one second signal from the pseudo signal.
    Type: Application
    Filed: September 9, 2013
    Publication date: March 12, 2015
    Applicant: APPLIED MICRO CIRCUITS CORPORATION
    Inventors: Francesco Caggioni, Dimitrios Giannakopoulos
  • Patent number: 8650464
    Abstract: A circuit and method form a codeword including parity and message bits, as follows. Each codeword has a first part in a current sequence (e.g. a current OTN-row) that is to be now transmitted and second part spread across multiple past sequences (e.g. previously prepared and transmitted OTN-rows). The codewords are grouped into multiple groups such that each codeword within a group has no bit in common with another codeword in that group. Moreover, each codeword has a bit in common with a different codeword in a different group.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: February 11, 2014
    Assignee: Applied Micro Circuits Corporation
    Inventors: Po Tong, Ivana Djurdjevic, Damien Latremouille, Francesco Caggioni, Dariush Dabiri
  • Patent number: 8205141
    Abstract: A system and method are provided for generating virtual lane (VL) forward error correction (FEC) overhead (OH) in a communication multi-lane distribution (MLD) protocol transmitter, and for recovering data words from virtual lanes with FEC OH in an MLD protocol receiver. The transmission method accepts an Optical Transport Network (OTN) frame with n consecutively ordered payload chunks of data words, at a first data rate. Each payload chunk is assigned to a virtual lane data word (VLDW) in an MLD frame of n consecutively ordered VLDWs. The assignment order of payload chunks to VLDWs is rotated at the start of each MLD frame. VLDWs are joined into VLDW groups, where each VLDW group includes at least one VLDW. FEC blocks are calculated for VLDWs, creating ordered VL codewords (VLCWs). Then, the VLCWs are multiplexed to maintain a consistent assignment of VLCW order to physical transmission lanes and transmitted.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: June 19, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventors: Francesco Caggioni, Tracy Xiaoming Ma
  • Patent number: 8160057
    Abstract: Systems and methods are provided for multi-channel ITU G.709 optical transport network (OTN) communications. The transmission method accepts an ITU G.709 OTN frame including an OTU overhead (OH) section and an ODU section. A forward error correction (FEC) parity section with a training signal is appended to the ITU G.709 OTN frame, to create a training-enhanced (TE) OTN frame. All, or a portion of the TE OTN may be buffered in a tangible memory medium in preparation for striping. The training-enhanced OTN frame is then striped into n parallel streams, and n TE_OTN-PFs (Parallel Frames) are supplied.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: April 17, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventors: Francesco Caggioni, Omer Acikel, Keith Conroy
  • Patent number: 8125979
    Abstract: Systems and methods are provided for multi-channel ITU G.709 optical transport network (OTN) transmission and receiving. The transmission method accepts a canonical ITU G.709 OTN frame including an OTU overhead (OH) section, an ODU section, and a forward error correction (FEC) parity section. A training signal wrapper is added to the ITU G.709 OTN frame, and at least a portion of a training-enhanced (TE) OTN frame is buffered in a tangible memory medium in preparation for striping. The method stripes the training-enhanced OTN frame into n parallel streams to supply n TE_OTN-PFs (Parallel Frames) at an output.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: February 28, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventors: Francesco Caggioni, Omer Acikel, Keith Conroy
  • Patent number: 7970285
    Abstract: A system and method are provided for calibrating temporal skew in a multichannel optical transport network (OTN) transmission device. The method accepts a pair of 2n-phase shift keying (2n-PSK) modulated signals, as well as a pair of 2p-PSK modulated signals. The 2n-PSK and 2p-PSK signals are converted to 2n-PSK and 2p-PSK optical signals, respectively. The 2n-PSK and 2p-PSK optical signals are orthogonally polarized and transmitted. A timing voltage is generated that is responsive to the intensity of the orthogonally polarized signals. The timing voltage is correlated to a reference frame calibration pattern associated with a preamble/header portion of an OTN frame. Then, the timing voltages associated with the Ix, Qx, Iy, and Qy signal paths are compared, and the misalignment between the timing voltages and the reference frame calibration pattern is minimized in response to adjusting time delay modules in the Ix, Qx, Iy, and Qy signal paths.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: June 28, 2011
    Assignee: Applied Micro Circuits Corporation
    Inventors: Keith Conroy, Omer Acikel, Francesco Caggioni
  • Patent number: 7965941
    Abstract: A system and method are provided for controlling time delay in a multichannel optical transport network (OTN) transmission device using time domain reflectometry (TDR) measurements. The method accepts a pair of 2n-phase shift keying (2n-PSK) modulated signals via Ix and Qx electrical signal paths, where n>1. Likewise, a pair of 2p-PSK modulated signals are accepted via Iy and Qy electrical signal paths where p>1. Using TDR modules, signal reflections are measured from an output port for each signal path. The method minimizes time delay differences in the signal reflections for the Ix, Qx, Iy, and Qy signals paths by using the signal reflection measurements to adjust time delay modules in each signal path.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: June 21, 2011
    Assignee: Applied Micro Circuits Corporation
    Inventors: Keith Conroy, Omer Acikel, Francesco Caggioni
  • Patent number: 7965946
    Abstract: A system and method are provided for calibrating skew in a multichannel optical transport network (OTN) transmission device. The method accepts a pair of 2n-phase shift keying (2nPSK) modulated signals via Ix and Qx electrical signal paths, where n>1. Likewise, a pair of 2p-PSK modulated signals are accepted via Iy and Qy electrical signal paths where p>1. The Ix, Qx, Iy, and Qy signals are correlated to a preamble/header portion of an OTN frame. A voltage on the Ix signal path is compared with Qx, and VO12 voltage is generated. A voltage on the Iy signal path is compared with Qy, and VO34 is generated. One of the Ix or Qx voltages is compared with one of Iy or Qy voltages to generate VOxy. Then, the VO voltages are minimized in response to adjusting time delay modules in the Ix, Qx, Iy, and Qy signals paths.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: June 21, 2011
    Assignee: Applied Micro Circuits Corporation
    Inventors: Keith Conroy, Omer Acikel, Francesco Caggioni