Patents by Inventor Francesco Carrara
Francesco Carrara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230223362Abstract: A package comprising a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate includes a dielectric layer and a plurality of interconnects. The plurality of interconnects includes a first plurality of interconnects configured as a first inductor and a second plurality of interconnects configured as a second inductor. The first integrated device is configured to be coupled to the first inductor. The second integrated device is configured to be coupled to the second inductor. The second integrated device is configured to tune the first inductor through the second inductor.Type: ApplicationFiled: January 13, 2022Publication date: July 13, 2023Inventors: FNU SURAJ PRAKASH, Paragkumar Ajaybhai THADESAR, John Jong-Hoon LEE, Nikhil RAMAN, Peng SONG, Francesco CARRARA
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Patent number: 11626336Abstract: A package that includes a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; a device located over the solder resist layer such that a portion of the device touches the solder resist layer; and an encapsulation layer located over the solder resist layer such that the encapsulation layer encapsulates the device. The solder resist layer is configured as a seating plane for the device. The device is located over the solder resist layer such that a surface of the device facing the substrate is approximately parallel to the first surface of the substrate. The solder resist layer includes at least one notch. The device is located over the solder resist layer such that at least one corner of the device touches the at least one notch.Type: GrantFiled: October 1, 2019Date of Patent: April 11, 2023Assignee: QUALCOMM IncorporatedInventors: Daniel Garcia, Kinfegebriel Amera Mengistie, Francesco Carrara, Chang-Ho Lee, Ashish Alawani, Mark Kuhlman, John Jong-Hoon Lee, Jeongkeun Kim, Xiaoju Yu, Supatta Niramarnkarn
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Patent number: 11239158Abstract: An integrated circuit (IC) package comprising a first die, including an active layer opposite a backside surface of the first die supporting a plurality of backside pads is provided. The IC package also incorporates a package substrate coupled to the active layer. The package pads on the package substrate correspond to the plurality of backside pads. A passive device comprising a plurality of wire bonds is coupled to the plurality of backside pads and the plurality of package pads. The passive device may also comprise a plurality of wire bonds coupled to the package pads by through silicon vias (TSVs). Multiple dies may be coupled with die-to-die wire bonds coupled to backside pads on each die.Type: GrantFiled: October 8, 2020Date of Patent: February 1, 2022Assignee: QUALCOMM IncorporatedInventors: Paragkumar Ajaybhai Thadesar, Changhan Hobie Yun, Sameer Sunil Vadhavkar, Daniel Daeik Kim, Francesco Carrara
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Publication number: 20210375732Abstract: Certain aspects of the present disclosure generally relate to a dielectric removal methodology and a metal patterning approach to allow partial embedding of electronic components (e.g., surface mount devices (SMDs)) in a substrate. By partially embedding relatively taller SMDs, the overall height of an electronic device may be reduced.Type: ApplicationFiled: June 2, 2020Publication date: December 2, 2021Inventors: Paragkumar Ajaybhai THADESAR, Sameer Sunil VADHAVKAR, Francesco CARRARA, Daniel Daeik KIM
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Publication number: 20210098320Abstract: A package that includes a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; a device located over the solder resist layer such that a portion of the device touches the solder resist layer; and an encapsulation layer located over the solder resist layer such that the encapsulation layer encapsulates the device. The solder resist layer is configured as a seating plane for the device. The device is located over the solder resist layer such that a surface of the device facing the substrate is approximately parallel to the first surface of the substrate. The solder resist layer includes at least one notch. The device is located over the solder resist layer such that at least one corner of the device touches the at least one notch.Type: ApplicationFiled: October 1, 2019Publication date: April 1, 2021Inventors: Daniel GARCIA, Kinfegebriel Amera MENGISTIE, Francesco CARRARA, Chang-Ho LEE, Ashish ALAWANI, Mark KUHLMAN, John Jong-Hoon LEE, Jeongkeun KIM, Xiaoju YU, Supatta NIRAMARNKARN
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Patent number: 10608598Abstract: In an example aspect, an apparatus includes a balanced power amplifier, which performs amplification in the presence of a variable antenna impedance. The balanced power amplifier includes a quadrature output power combiner coupled to a first power amplifying path and a second power amplifying path, detection circuitry, and control circuitry. The detection circuitry includes at least one power detector coupled to an isolated port of the quadrature output power combiner and a resistor coupled between the isolated port and a ground. The at least one power detector is configured to measure power at the isolated port, which is based on a resistance of the resistor. The control circuitry is configured to adjust operating conditions of a first power amplifier of the first power amplifying path and the second power amplifier of the second power amplifying path based on the power that is measured at the isolated port.Type: GrantFiled: June 28, 2018Date of Patent: March 31, 2020Assignee: QUALCOMM Technologies, Inc.Inventors: Chuan Wang, Li Liu, Kevin Hsi Huai Wang, Bhushan Shanti Asuri, Gurkanwal Sahota, Francesco Carrara
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Publication number: 20200007092Abstract: An apparatus is disclosed for amplification in presence of a variable antenna impedance. In an example aspect, the apparatus comprises a balanced power amplifier, which includes a quadrature output power combiner coupled to a first power amplifying path and a second power amplifying path, detection circuitry, and control circuitry. The detection circuitry includes at least one power detector coupled to an isolated port of the quadrature output power combiner and a resistor coupled between the isolated port and a ground. The at least one power detector is configured to measure power at the isolated port, which is based on a resistance of the resistor. The control circuitry is configured to adjust operating conditions of a first power amplifier of the first power amplifying path and the second power amplifier of the second power amplifying path based on the power that is measured at the isolated port.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Inventors: Chuan Wang, Li Liu, Kevin Hsi Huai Wang, Bhushan Shanti Asuri, Gurkanwal Sahota, Francesco Carrara
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Patent number: 10490621Abstract: Apparatus implementing various structures to decrease the distance between two inductive elements for tuning an inductance with greater variability (a wider tuning range). One example integrated circuit (IC) package generally includes a laminate, a solder resist layer disposed on an upper surface of the laminate, and a semiconductor die disposed above the laminate and comprising a first inductor. At least a portion of a second inductor is disposed above a section of the solder resist layer, the first inductor at least partially overlaps the second inductor, and there is a gap between the first inductor and the second inductor.Type: GrantFiled: July 30, 2018Date of Patent: November 26, 2019Assignee: QUALCOMM IncorporatedInventors: Paragkumar Ajaybhai Thadesar, Mario Francisco Velez, Changhan Hobie Yun, Francesco Carrara, Jonghae Kim, Xiaoju Yu, Niranjan Sunil Mudakatte
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Patent number: 10135399Abstract: A common-mode feedback circuit includes a transconductor input stage with differential input terminals, and a frequency-compensated gain stage coupled to the transconductor input stage with differential output terminals. The common-mode feedback circuit also includes a feedback loop having a comparator configured to produce a feedback error signal for the transconductor input stage by comparing with a reference a common-mode sensing signal indicative of a common-mode voltage level sensed at the differential output terminals. In addition, the common-mode feedback loop includes a converter for converting the common-mode voltage level sensed at said differential output terminals into a current signal coupled to the comparator.Type: GrantFiled: February 24, 2017Date of Patent: November 20, 2018Assignee: STMICROELECTRONICS S.R.L.Inventors: Francesco Carrara, Felice Alberto Torrisi, Francesco Clerici
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Publication number: 20170163222Abstract: A common-mode feedback circuit includes a transconductor input stage with differential input terminals, and a frequency-compensated gain stage coupled to the transconductor input stage with differential output terminals. The common-mode feedback circuit also includes a feedback loop having a comparator configured to produce a feedback error signal for the transconductor input stage by comparing with a reference a common-mode sensing signal indicative of a common-mode voltage level sensed at the differential output terminals. In addition, the common-mode feedback loop includes a converter for converting the common-mode voltage level sensed at said differential output terminals into a current signal coupled to the comparator.Type: ApplicationFiled: February 24, 2017Publication date: June 8, 2017Inventors: Francesco Carrara, Felice Alberto Torrisi, Francesco Clerici
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Patent number: 9628028Abstract: A common-mode feedback circuit includes a transconductor input stage with differential input terminals, and a frequency-compensated gain stage coupled to the transconductor input stage with differential output terminals. The common-mode feedback circuit also includes a feedback loop having a comparator configured to produce a feedback error signal for the transconductor input stage by comparing with a reference a common-mode sensing signal indicative of a common-mode voltage level sensed at the differential output terminals. In addition, the common-mode feedback loop includes a converter for converting the common-mode voltage level sensed at said differential output terminals into a current signal coupled to the comparator.Type: GrantFiled: June 22, 2015Date of Patent: April 18, 2017Assignee: STMICROELECTRONICS S.R.L.Inventors: Francesco Carrara, Felice Alberto Torrisi, Francesco Clerici
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Publication number: 20160072448Abstract: A common-mode feedback circuit includes a transconductor input stage with differential input terminals, and a frequency-compensated gain stage coupled to the transconductor input stage with differential output terminals. The common-mode feedback circuit also includes a feedback loop having a comparator configured to produce a feedback error signal for the transconductor input stage by comparing with a reference a common-mode sensing signal indicative of a common-mode voltage level sensed at the differential output terminals. In addition, the common-mode feedback loop includes a converter for converting the common-mode voltage level sensed at said differential output terminals into a current signal coupled to the comparator.Type: ApplicationFiled: June 22, 2015Publication date: March 10, 2016Inventors: Francesco CARRARA, Felice Alberto TORRISI, Francesco CLERICI
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Patent number: 8278970Abstract: A device for detecting the peak value of a signal with crest factor not known a priori includes a pair of peak detectors, each of which includes a rectifier element and a discharge-current generator and generates a respective output signal that is a function of the ratio between a physical dimension of the rectifier element and the intensity of discharge current produced by the generator. The ratio is different for the two detectors, and a combination network combines the output signals of the two peak detectors with one another and produces a combined signal indicating the peak value sought with high accuracy.Type: GrantFiled: January 25, 2011Date of Patent: October 2, 2012Assignee: ST-Ericsson SAInventors: Calogero Davide Presti, Francesco Carrara, Antonino Scuderi, Giuseppe Palmisano
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Patent number: 8004368Abstract: A digital amplitude modulator. The digital amplitude modulator is configured to modulate the amplitude of an input carrier signal based on input digital data and generate a corresponding output signal. The digital amplitude modulator includes a first variable gain amplifier for receiving the input carrier signal and generating a corresponding first amplified carrier signal, a second variable gain amplifier for receiving the input digital data and generating corresponding digital amplitude control data and a plurality of selectively activatable amplifier stages. Each amplifier stage receives a replica of the first amplified carrier signal and generates a corresponding second amplified carrier signal when activated. The output signal corresponds to a combination of the second amplified carrier signals generated by the activated amplifier stages.Type: GrantFiled: September 15, 2009Date of Patent: August 23, 2011Assignee: STMicroelectronics, S.r.l.Inventors: Calogero Davide Presti, Francesco Carrara, Antonino Scuderi, Guiseppe Palmisano
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Publication number: 20110115525Abstract: A device for detecting the peak value of a signal with crest factor not known a priori includes a pair of peak detectors, each of which includes a rectifier element and a discharge-current generator and generates a respective output signal that is a function of the ratio between a physical dimension of the rectifier element and the intensity of discharge current produced by the generator. The ratio is different for the two detectors, and a combination network combines the output signals of the two peak detectors with one another and produces a combined signal indicating the peak value sought with high accuracy.Type: ApplicationFiled: January 25, 2011Publication date: May 19, 2011Applicant: ST-Ericsson SAInventors: Calogero Davide PRESTI, Francesco Carrara, Antonino Scuderi, Giuseppe Palmisano
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Patent number: 7880508Abstract: A device for detecting the peak value of a signal with crest factor not known a priori includes a pair of peak detectors, each of which includes a rectifier element and a discharge-current generator and generates a respective output signal that is a function of the ratio between a physical dimension of the rectifier element and the intensity of discharge current produced by the generator. The ratio is different for the two detectors, and a combination network combines the output signals of the two peak detectors with one another and produces a combined signal indicating the peak value sought with high accuracy.Type: GrantFiled: June 13, 2007Date of Patent: February 1, 2011Assignee: ST-Ericsson SAInventors: Calogero Davide Presti, Francesco Carrara, Antonino Scuderi, Giuseppe Palmisano
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Patent number: 7795989Abstract: A circuit matches the load impedance of an electronic device. The circuit comprises an impedance network, a control circuit suitable for varying the impedance of said network and a sensor coupled with said network and said load and suitable for detecting the ratio between the incident and reflected standing waves in transferring power from the electronic device to the load; the sensor is suitable for providing two signals substantially proportional to the incident and reflected amplitude of the waves at the control circuit. The impedance network is a network of variable resistances and the control circuit is suitable for varying the value of the resistances to lower said ratio between the incident and reflected standing waves to a value that ensures the transfer of power from the electronic device to the load.Type: GrantFiled: January 31, 2008Date of Patent: September 14, 2010Assignee: STMicroelectronics S.r.l.Inventors: Antonino Scuderi, Francesco Carrara, Calogero Davide Presti, Giuseppe Palmisano
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Patent number: 7759983Abstract: A device for comparing the peak value of a periodic voltage signal or a linear combination of periodic voltage signals with a reference voltage includes a reference transconductor element for converting the reference voltage into a reference current, respective transconductor elements for converting each of the periodic voltage signals into respective periodic current signals, a current-comparison node for comparing the respective periodic current signals with the reference current, generating a comparison current as a difference between the sum of the aforesaid periodic current signals and the reference current, a current rectifier supplied with the comparison current, a hold capacitor charged with the output current of the current rectifier, and a discharge-current generator in parallel to the hold capacitor.Type: GrantFiled: July 17, 2007Date of Patent: July 20, 2010Assignee: ST-Ericsson SAInventors: Francesco Carrara, Calogero Davide Presti, Antonino Scuderi, Carmelo Santagati, Giuseppe Palmisano
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Publication number: 20100109789Abstract: A digital amplitude modulator is configured to modulate the amplitude of an input carrier signal based on input digital data and generate a corresponding output signal. The digital amplitude modulator includes a first variable gain amplifier for receiving the input carrier signal and generating a corresponding first amplified carrier signal, a second variable gain amplifier for receiving the input digital data and generating corresponding digital amplitude control data and a plurality of selectively activatable amplifier stages. Each amplifier stage receives a replica of the first amplified carrier signal and generates a corresponding second amplified carrier signal when activated. The output signal corresponds to a combination of the second amplified carrier signals generated by the activated amplifier stages.Type: ApplicationFiled: September 15, 2009Publication date: May 6, 2010Applicant: STMicroelectronics S.r.l.Inventors: Calogero Davide Presti, Francesco Carrara, Antonino Scuderi, Giuseppe Palmisano
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Publication number: 20080186105Abstract: A circuit matches the load impedance of an electronic device. The circuit comprises an impedance network, a control circuit suitable for varying the impedance of said network and a sensor coupled with said network and said load and suitable for detecting the ratio between the incident and reflected standing waves in transferring power from the electronic device to the load; the sensor is suitable for providing two signals substantially proportional to the incident and reflected amplitude of the waves at the control circuit. The impedance network is a network of variable resistances and the control circuit is suitable for varying the value of the resistances to lower said ratio between the incident and reflected standing waves to a value that ensures the transfer of power from the electronic device to the load.Type: ApplicationFiled: January 31, 2008Publication date: August 7, 2008Applicant: STMicroelectronics S.r.l.Inventors: Antonino Scuderi, Francesco Carrara, Calogero Davide Presti, Giuseppe Palmisano