Abstract: In accordance with an embodiment, a method for operating a successive approximation ADC comprising a first capacitor array includes measuring a first weight of an MSB-ath bit of the ADC by applying a first reference voltage to first terminals of capacitors of the first capacitor array corresponding to the MSB-ath bit, applying a second reference voltage to first terminals of capacitors of the first capacitor array corresponding to significant bits lower than the MSB-ath bit, applying the first reference voltage to first terminals of a first set of capacitors of the first capacitor array corresponding to significant bits higher than the MSB-ath bit, and applying the second reference voltage to first terminals of a second set of capacitors of the first capacitor array corresponding to the significant bits higher than the MSB-ath bit; subsequently, a weight of a capacitance of the capacitors corresponding to the MSB-ath bit is successively approximated.

Abstract: In accordance with an embodiment, a method for digital-to-analog conversion includes: mapping a uniformly distributed input code to a non-uniformly distributed input code of a switched capacitor digital-to-analog converter (DAC), the non-uniformly distributed input code including a most significant code (MSC) and a least significant code (LSC); transferring a first charge from a set of DAC capacitors to a charge accumulator based on the MSC; forming a second charge based on the LSC; and transferring the second charge from the set of DAC capacitors to the charge accumulator, where each capacitor of the set of DAC capacitors is used for each value of the non-uniformly distributed input code, each capacitor of the set of DAC capacitors provides a same corresponding nominal charge within each value of the non-uniformly distributed input code, and where the same nominal charge is proportional to a value of the non-uniformly distributed input code.

Abstract: In accordance with an embodiment, a method for operating a successive approximation ADC comprising a first capacitor array includes measuring a first weight of an MSB-ath bit of the ADC by applying a first reference voltage to first terminals of capacitors of the first capacitor array corresponding to the MSB-ath bit, applying a second reference voltage to first terminals of capacitors of the first capacitor array corresponding to significant bits lower than the MSB-ath bit, applying the first reference voltage to first terminals of a first set of capacitors of the first capacitor array corresponding to significant bits higher than the MSB-ath bit, and applying the second reference voltage to first terminals of a second set of capacitors of the first capacitor array corresponding to the significant bits higher than the MSB-ath bit; subsequently, a weight of a capacitance of the capacitors corresponding to the MSB-ath bit is successively approximated.

Abstract: In accordance with an embodiment, a method for operating a successive approximation ADC comprising a first capacitor array includes measuring a first weight of an MSB-ath bit of the ADC by applying a first reference voltage to first terminals of capacitors of the first capacitor array corresponding to the MSB-ath bit, applying a second reference voltage to first terminals of capacitors of the first capacitor array corresponding to significant bits lower than the MSB-ath bit, applying the first reference voltage to first terminals of a first set of capacitors of the first capacitor array corresponding to significant bits higher than the MSB-ath bit, and applying the second reference voltage to first terminals of a second set of capacitors of the first capacitor array corresponding to the significant bits higher than the MSB-ath bit; subsequently, a weight of a capacitance of the capacitors corresponding to the MSB-ath bit is successively approximated.

Abstract: In accordance with an embodiment, a method for digital-to-analog conversion includes: mapping a uniformly distributed input code to a non-uniformly distributed input code of a switched capacitor digital-to-analog converter (DAC), the non-uniformly distributed input code including a most significant code (MSC) and a least significant code (LSC); transferring a first charge from a set of DAC capacitors to a charge accumulator based on the MSC; forming a second charge based on the LSC; and transferring the second charge from the set of DAC capacitors to the charge accumulator, where each capacitor of the set of DAC capacitors is used for each value of the non-uniformly distributed input code, each capacitor of the set of DAC capacitors provides a same corresponding nominal charge within each value of the non-uniformly distributed input code, and where the same nominal charge is proportional to a value of the non-uniformly distributed input code.

Abstract: In accordance with an embodiment, a method for digital-to-analog conversion includes: mapping a uniformly distributed input code to a non-uniformly distributed input code of a switched capacitor digital-to-analog converter (DAC), the non-uniformly distributed input code including a most significant code (MSC) and a least significant code (LSC); transferring a first charge from a set of DAC capacitors to a charge accumulator based on the MSC; forming a second charge based on the LSC; and transferring the second charge from the set of DAC capacitors to the charge accumulator, where each capacitor of the set of DAC capacitors is used for each value of the non-uniformly distributed input code, each capacitor of the set of DAC capacitors provides a same corresponding nominal charge within each value of the non-uniformly distributed input code, and where the same nominal charge is proportional to a value of the non-uniformly distributed input code.

Abstract: In accordance with an embodiment, a method for digital-to-analog conversion includes: mapping a uniformly distributed input code to a non-uniformly distributed input code of a switched capacitor digital-to-analog converter (DAC), the non-uniformly distributed input code including a most significant code (MSC) and a least significant code (LSC); transferring a first charge from a set of DAC capacitors to a charge accumulator based on the MSC; forming a second charge based on the LSC; and transferring the second charge from the set of DAC capacitors to the charge accumulator, where each capacitor of the set of DAC capacitors is used for each value of the non-uniformly distributed input code, each capacitor of the set of DAC capacitors provides a same corresponding nominal charge within each value of the non-uniformly distributed input code, and where the same nominal charge is proportional to a value of the non-uniformly distributed input code.

Abstract: In some examples, a device can be used for measuring the impedance of a first battery cell. The device includes a first analog-to-digital converter (ADC) and a second ADC. The device also includes a multiplexer configured to connect the first ADC to the first battery cell in a first instance and to connect the second ADC to a current sensor in the first instance. The current sensor is configured to sense current through the first battery cell. The multiplexer is also configured to connect the first ADC to the current sensor in a second instance and to connect the second ADC to the first battery cell in the second instance or in a third instance.

Abstract: A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift ??. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor wi,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor wi,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters.

Abstract: In accordance with an embodiment, a circuit includes a current digital-to-analog converter (DAC) having a current switching network coupled to a current DAC output, a first cascode current source coupled between a first supply node and the current switching network, a second cascode current source between a second supply node and the current switching network, and a shorting switch coupled between a first cascode node of the first cascode current source, and a second cascode node of the second cascode current source.

Abstract: In some examples, a device can be used for measuring the impedance of a first battery cell. The device includes a first analog-to-digital converter (ADC) and a second ADC. The device also includes a multiplexer configured to connect the first ADC to the first battery cell in a first instance and to connect the second ADC to a current sensor in the first instance. The current sensor is configured to sense current through the first battery cell. The multiplexer is also configured to connect the first ADC to the current sensor in a second instance and to connect the second ADC to the first battery cell in the second instance or in a third instance.

Abstract: A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift ??. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor wi,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor wi,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters.

Abstract: A method of operating a redundant successive approximation analog-to-digital converter (ADC) includes: sampling an input signal; and successively approximating the sampled input signal using a digital-to-analog converter (DAC) including DAC reference elements having at least one sub-binary weighted DAC reference element. Successively approximating the sampled input signal includes performing a plurality of successive approximation cycles.

Abstract: Methods adapted for digital-to-analog conversion compensation and systems are described. In a compensation method, inputs of a digital-to-analog converter (DAC) are adjusted to provide an even number inputs for the DAC. Further, one or more analog input signals are converted to generate one or more corresponding digital output signals. The one or more digital output signals are compensated to compensate for the adjustment of the inputs of the DAC.

Abstract: Methods adapted for digital-to-analog conversion compensation and systems are described. In a compensation method, inputs of a digital-to-analog converter (DAC) are adjusted to provide an even number inputs for the DAC. Further, one or more analog input signals are converted to generate one or more corresponding digital output signals. The one or more digital output signals are compensated to compensate for the adjustment of the inputs of the DAC.

Abstract: Some embodiments include apparatus and methods using an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC), a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, and a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC.

Abstract: Some embodiments include apparatus and methods using an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC), a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, and a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC.

Abstract: Some embodiments include apparatus and methods using an integrator in a loop filter of a sigma-delta analog-to-digital converter (ADC), a digital-to-analog converter (DAC) located on a feedback path of the ADC, the DAC including output nodes coupled to input nodes of the integrator, and a comparator including input nodes to receive signals from output nodes of the integrator, and an output node to provide information during calibration of the DAC.