Abstract: A sigma-delta ADC comprising: a first-input-resistor connected in series between a first-input-terminal and a first-feedback-node; a second-input-resistor connected in series between a second-input-terminal and a second-feedback-node; a third-input-resistor connected in series between a third-input-terminal and a third-feedback-node; a first-multiplexer-switch connected in series between the first-feedback-node and a first-amplifier-second-input-terminal; a second-multiplexer-switch connected in series between the second-feedback-node and a first-amplifier-first-input-terminal; a third-multiplexer-switch connected in series between the third-feedback-node and the first-amplifier-second-input-terminal; a first-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to a reference-terminal; a second-feedback-current-source having a first terminal and second terminal, wherein the second terminal is connected to the reference-terminal; a first-feedback-selecti

Abstract: There is described a method of verifying a function of a power supply monitor in a digital control system, wherein the power supply monitor is adapted to monitor whether or not a power supply voltage is between a lower threshold value and an upper threshold value. The method comprises: setting the power supply voltage to a first value, the first value being below the lower threshold value, checking, as a first check, that the power supply monitor indicates that the power supply voltage is below the lower threshold value, setting the power supply voltage to a second value, the second value being above the lower threshold value and below the upper threshold value, checking, as a second check, that the power supply monitor indicates that the power supply voltage is above the lower threshold value, and verifying the function of the power supply monitor if both the first check and the second check are successful. There is also described a corresponding device and computer program.

Abstract: A system for register error detection is described, the system comprising: a plurality of addressable registers comprising sets of registers, the registers in each set having contiguous addresses; a cyclic redundancy check generator coupled to the addressable registers and configured to determine a cyclic-redundancy-check result for each set of registers from the values of each of the respective set of registers; a controller coupled to the registers and the cyclic-redundancy-check generator.

Abstract: A system for register error detection is described, the system comprising: a plurality of addressable registers comprising sets of registers, the registers in each set having contiguous addresses; a cyclic redundancy check generator coupled to the addressable registers and configured to determine a cyclic-redundancy-check result for each set of registers from the values of each of the respective set of registers; a controller coupled to the registers and the cyclic-redundancy-check generator.