Abstract: Binary message signals arriving over a PCM link at a retransmitting station, with a predetermined average bit cadence subject to random variations, are cyclically written in an 8-stage buffer register under the control of an 8-pulse writing counter stepped by clock pulses extracted from the incoming bit stream. The contents of the buffer register are read out under the control of an 8-pulse reading counter stepped by a local pulse generator whose pulse rate substantially corresponds to the predetermined cadence. Any deviations of the actual bit rate from the predetermined cadence are detected in a phase comparator receiving mutually interleaved monitoring pulses, once per 8-bit cycle, from the two counters.

Abstract: Four bit streams arriving simultaneously over respective incoming lines at a transmitting terminal, connected via a PCM link with a remote receiving terminal, constitute recurrent lower-order frames whose bits are to be interleaved in a composite higher-order frame to be sent on to the remote terminal for redistribution over four outgoing lines. The bits of each incoming bit stream are cyclically written in an 8-stage buffer register at their rate of arrival, the contents of the register stages being read out at a higher rate to allow for the interpolation of ancillary bits constituting supervisory signals. Each higher-order frame consists of four subframes in which the message bits from the contributing bit streams are preceded by one or more ancillary bits; the latter include a discriminating bit in each of the last three subframes indicating whether or not a further bit in the fourth subframe is a stuffing bit or a message bit. The insertion of a stuffing bit, i.e.