Abstract: Various implementations are directed to systems and methods for maintaining integrity and reliability of data in an SSD device using error correction coding. According to certain aspects, for frames of data having an ECC code with two or more sub-codes, while one sub-decoder is not in use it could be used to start a decode of another frame. By “interleaving” and alternating the frames between sub-decoders, two or more frames can be decoded simultaneously in an efficient manner. This can clearly be extended to more sub-codes (i.e. dimensions greater than two).

Abstract: Various implementations are directed to systems and methods for maintaining integrity and reliability of data in an SSD device using error correction coding. According to certain aspects, for frames of data having an ECC code with two or more sub-codes, while one sub-decoder is not in use it could be used to start a decode of another frame. By “interleaving” and alternating the frames between sub-decoders, two or more frames can be decoded simultaneously in an efficient manner. This can clearly be extended to more sub-codes (i.e. dimensions greater than two).

Abstract: Various implementations are directed to systems and methods for maintaining integrity and reliability of data in an SSD device using error correction coding. According to certain aspects, for frames of data having an ECC code with two or more sub-codes, while one sub-decoder is not in use it could be used to start a decode of another frame. By “interleaving” and alternating the frames between sub-decoders, two or more frames can be decoded simultaneously in an efficient manner. This can clearly be extended to more sub-codes (i.e. dimensions greater than two).

Abstract: There is provided a method of providing adjusted LLR values of a plurality of bits in a codeword to an LDPC decoder, the plurality of bits representing a plurality of charge states of a plurality of memory cells of a non-volatile memory. The method comprises storing in a non-volatile memory controller associated with the non-volatile memory LLR values of the plurality of bits. The controller then determines a plurality of levels of the charge states represented by the plurality of bits. The controller then generates, by a distribution processor, distributions of a population of the plurality of bits in the codeword at each of the plurality of levels at a first and a second time after the first time. The controller then generates the adjusted LLR values based on a comparison between the first and second distributions, and then decodes the codeword according to the adjusted LLR values.

Abstract: There is provided a method of providing adjusted LLR values of a plurality of bits in a codeword to an LDPC decoder, the plurality of bits representing a plurality of charge states of a plurality of memory cells of a non-volatile memory. The method comprises storing in a non-volatile memory controller associated with the non-volatile memory LLR values of the plurality of bits. The controller then determines a plurality of levels of the charge states represented by the plurality of bits. The controller then generates, by a distribution processor, distributions of a population of the plurality of bits in the codeword at each of the plurality of levels at a first and a second time after the first time. The controller then generates the adjusted LLR values based on a comparison between the first and second distributions, and then decodes the codeword according to the adjusted LLR values.

Abstract: Various implementations described herein relate to systems and methods for correcting data from memory systems such as a plurality of non-volatile memory devices of a Solid State Drive (SSD), including but not limited to, receiving frames of the data from the plurality of non-volatile memory devices, allocating the frames among pooled frontline Error Correction Code (ECC) decoders, decoding, by the pooled frontline ECC decoders, the frames to output first decoded frames, and returning the first decoded frames to the read channels.

Abstract: Various implementations are directed to systems and methods for maintaining integrity and reliability of data in an SSD device using error correction coding. According to certain aspects, for frames of data having an ECC code with two or more sub-codes, while one sub-decoder is not in use it could be used to start a decode of another frame. By “interleaving” and alternating the frames between sub-decoders, two or more frames can be decoded simultaneously in an efficient manner. This can clearly be extended to more sub-codes (i.e. dimensions greater than two).

Abstract: A method for fast calculation of a frame error rate (FER) of an error correcting code (ECC) soft decoder using a soft read process includes determining an MI-FER conversion data structure based on a relationship between mutual information (MI) of input channels and output channels of a memory, and FER of the ECC soft decoder, and decoding an encoded data codeword stored in a memory page of the memory and read using a soft read process. The method further includes generating a set of joint probability values using the information from the soft read process and data indicating true bit values for the data codeword, determining an MI value using the set of joint probability values, and determining an FER estimate using the MI-FER conversion data structure.

Abstract: Various implementations described herein relate to systems and methods for correcting data from memory systems such as a plurality of non-volatile memory devices of a Solid State Drive (SSD), including but not limited to, receiving frames of the data from the plurality of non-volatile memory devices, allocating the frames among pooled frontline Error Correction Code (ECC) decoders, decoding, by the pooled frontline ECC decoders, the frames to output first decoded frames, and returning the first decoded frames to the read channels.

Abstract: A solid state storage device comprises a non-volatile memory controller configured to store data in a non-volatile memory, wherein the stored data is encoded using a first error-correcting code and a second Low Density Parity Check (LDPC) code. The non-volatile memory controller includes a hard-decision LDPC decoder to decode encoded data received from the non-volatile memory and provide a decoded data output. The hard-decision LDPC decoder selects a voting scheme at each iteration in a sequence of iterations of decoding to determine when to implement bit flipping at a variable node amongst a plurality of check nodes, each of the plurality of check nodes connected to a plurality of variable nodes.

Abstract: A method of providing, by a controller, a log likelihood ratio (LLR) to a low-density parity check (LDPC) decoder, the method comprising storing, in a non-volatile memory controller, a look-up table for storing LLR values of at least one bit representing a charge state of a cell of the plurality of cells in the memory. The controller determines a cell charge state of the target cell, calculates a value representative of the difference in charge states of the target cell and at least one of a plurality of neighboring cells. The controller compares the calculated value with at least one predetermined threshold value, and sets at least one address bit of an address to the look-up table if the calculated value exceeds the at least one threshold value. The controller extracts a new LLR value from the look-up table, and provides the new LLR value to the LDPC decoder.

Abstract: A method of providing, by a controller, a log likelihood ratio (LLR) to a low-density parity check (LDPC) decoder, the method comprising storing, in a non-volatile memory controller, a look-up table for storing LLR values of at least one bit representing a charge state of a cell of the plurality of cells in the memory. The controller determines a cell charge state of the target cell, calculates a value representative of the difference in charge states of the target cell and at least one of a plurality of neighboring cells. The controller compares the calculated value with at least one predetermined threshold value, and sets at least one address bit of an address to the look-up table if the calculated value exceeds the at least one threshold value. The controller extracts a new LLR value from the look-up table, and provides the new LLR value to the LDPC decoder.

Abstract: A solid state storage device comprises a non-volatile memory controller configured to store data in a non-volatile memory, wherein the stored data is encoded using a first error-correcting code and a second Low Density Parity Check (LDPC) code. The non-volatile memory controller includes a hard-decision LDPC decoder to decode encoded data received from the non-volatile memory and provide a decoded data output. The hard-decision LDPC decoder selects a voting scheme at each iteration in a sequence of iterations of decoding to determine when to implement bit flipping at a variable node amongst a plurality of check nodes, each of the plurality of check nodes connected to a plurality of variable nodes.

Abstract: A device, which is autonomous or which can be associated with another structure, for propulsion in a liquid environment, is described. The device has a bladder body made of a soft material, developing along and around a central longitudinal axis, defining an internal chamber between a dorsal wall and a ventral wall; in the bladder body, an inlet opening and an outlet opening of a liquid in and out of the chamber, arranged at a longitudinal end of the body; and drive means for driving a contraction of the bladder, arranged on the dorsal wall and having a mechanical connection with the ventral to cyclically attract the ventral wall to the dorsal wall, thereby causing a pulsed ejection of a propeller jet from the chamber through the outlet opening.

Abstract: A device, which is autonomous or which can be associated with another structure, for propulsion in a liquid environment is described. The device has a bladder body made of a soft material, developing along and around a central longitudinal axis, defining an internal chamber between a dorsal wall and a ventral wall; in the bladder body, an inlet opening and an outlet opening of a liquid in and out of the chamber, arranged at a longitudinal end of the body; and drive means for driving a contraction of the bladder, arranged on the dorsal wall and having a mechanical connection with the ventral to cyclically attract the ventral wall to the dorsal wall, thereby causing a pulsed ejection of a propeller jet from the chamber through the outlet opening.