Patents by Inventor Francesco La Rosa

Francesco La Rosa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Individually read-accessible twin memory cells
    Patent number: 9653470
    Abstract: The present disclosure relates to a non-volatile memory on a semiconductor substrate, comprising: a first memory cell comprising a floating-gate transistor and a select transistor having an embedded vertical control gate, a second memory cell comprising a floating-gate transistor and a select transistor having the same control gate as the select transistor of the first memory cell, a first bit line coupled to the floating-gate transistor of the first memory cell, and a second bit line coupled to the floating-gate transistor of the second memory cell.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: May 16, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • VERTICAL BIPOLAR TRANSISTOR
    Publication number: 20170117326
    Abstract: The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.
    Type: Application
    Filed: January 4, 2017
    Publication date: April 27, 2017
    Inventors: Philippe Boivin, Francesco La Rosa, Julien Delalleau
  • Sense amplifier circuit with offset compensation for a non-volatile memory device
    Patent number: 9627011
    Abstract: A method for operating a non-volatile memory device uses a sense amplifier that includes a first branch and a second branch. During a pre-charging step, a bit line of a memory array of the non-volatile memory device is biased in order to pre-charge the bit line. During the pre-charging step, an offset between the first branch and the second branch is detected and stored. During a reading step subsequent to the pre-charging step, a cell current is received from the bit line at the first branch and a reference current is received from a current-reference structure at the second branch. During the reading step, and amplified voltage is generated as a function of the cell current and the reference current. During the reading step, an output voltage is generated based on the amplified voltage compensated by the offset stored during the pre-charging step.
    Type: Grant
    Filed: July 16, 2016
    Date of Patent: April 18, 2017
    Assignees: STMicroelectronics S.r.l., STMicroelectronics (Rousset) SAS
    Inventors: Antonino Conte, Francesco La Rosa
  • Twin memory cell interconnection structure
    Patent number: 9627068
    Abstract: Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: April 18, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Dual non-volatile memory cell comprising an erase transistor
    Patent number: 9613709
    Abstract: The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: April 4, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • NON-VOLATILE MEMORY WITH A VARIABLE POLARITY LINE DECODER
    Publication number: 20170084336
    Abstract: The present disclosure relates to a memory including a memory array with at least two rows of memory cells, a first driver coupled to a control line of the first row of memory cells, and a second driver coupled to a control line of the second row of memory cells. The first driver is made in a first well, the second driver is made in a second well electrically insulated from the first well, and the two rows of memory cells are produced in a memory array well electrically insulated from the first and second wells.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventor: Francesco La Rosa
  • VERTICAL MEMORY CELL WITH NON-SELF-ALIGNED FLOATING DRAIN-SOURCE IMPLANT
    Publication number: 20170084749
    Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventors: Marc MANTELLI, Stephan NIEL, Arnaud REGNIER, Francesco LA ROSA, Julien DELALLEAU
  • Vertical bipolar transistor
    Patent number: 9570513
    Abstract: The disclosure relates to an integrated circuit comprising a transistor comprising first and second conduction terminals and a control terminal. The integrated circuit further comprises a stack of a first dielectric layer, a conductive layer, and a second dielectric layer, the first conduction terminal comprising a first semiconductor region formed in the first dielectric layer, the control terminal comprising a second semiconductor region formed in the conductive layer, and the second conduction terminal comprising a third semiconductor region formed in the second dielectric layer.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: February 14, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Philippe Boivin, Francesco La Rosa, Julien Delalleau
  • DUAL NON-VOLATILE MEMORY CELL COMPRISING AN ERASE TRANSISTOR
    Publication number: 20170011804
    Abstract: The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Non-volatile memory with a variable polarity line decoder
    Patent number: 9543018
    Abstract: The present disclosure relates to a memory including a memory array with at least two rows of memory cells, a first driver coupled to a control line of the first row of memory cells, and a second driver coupled to a control line of the second row of memory cells. The first driver is made in a first well, the second driver is made in a second well electrically insulated from the first well, and the two rows of memory cells are produced in a memory array well electrically insulated from the first and second wells.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: January 10, 2017
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francesco La Rosa
  • Vertical memory cell with non-self-aligned floating drain-source implant
    Patent number: 9543311
    Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: January 10, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Marc Mantelli, Stephan Niel, Arnaud Regnier, Francesco La Rosa, Julien Delalleau
  • MEMORY CELL HAVING A VERTICAL SELECTION GATE FORMED IN AN FDSOI SUBSTRATE
    Publication number: 20160372561
    Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.
    Type: Application
    Filed: August 30, 2016
    Publication date: December 22, 2016
    Inventors: Arnaud Regnier, Jean-Michel Mirabel, Stephan Niel, Francesco La Rosa
  • Method and device for characterizing or measuring a floating capacitance
    Patent number: 9506964
    Abstract: The disclosure comprises: linking a first terminal of the capacitance to the mid-point of a first voltage divider bridge, applying a first voltage to a second terminal of the capacitance, maintaining a voltage of a mid-point of the first divider bridge near a reference voltage, and discharging a mid-point of a second divider bridge with a constant current. When a voltage of the mid-point of the second bridge reaches a first voltage threshold, applying a second voltage to the second terminal of the capacitance, and measuring the time for the voltage to reach a second threshold.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: November 29, 2016
    Assignee: STMICROELECTRONICS ROUSSET SAS
    Inventor: Francesco La Rosa
  • TWIN MEMORY CELL INTERCONNECTION STRUCTURE
    Publication number: 20160336070
    Abstract: Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline.
    Type: Application
    Filed: December 28, 2015
    Publication date: November 17, 2016
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Dual non-volatile memory cell comprising an erase transistor
    Patent number: 9484107
    Abstract: The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: November 1, 2016
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • MEMORY CELL COMPRISING NON-SELF-ALIGNED HORIZONTAL AND VERTICAL CONTROL GATES
    Publication number: 20160308011
    Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.
    Type: Application
    Filed: June 28, 2016
    Publication date: October 20, 2016
    Inventors: Francesco LA ROSA, Stephan NIEL, Julien DELALLEAU, Arnaud REGNIER
  • Page or word-erasable composite non-volatile memory
    Patent number: 9460798
    Abstract: A non-volatile memory includes bit lines, a first page-erasable sector including memory cells of a first type, and a second word-erasable or bit-erasable sector including memory cells of a second type. The memory cells of the first type comprise a single floating-gate transistor and the memory cells of the second type comprise a first floating-gate transistor and a second floating-gate transistor the floating gates of which are electrically coupled, the second floating-gate transistor of a memory cell of the second type enabling the memory cell to be individually erased.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: October 4, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francesco La Rosa
  • Lower power sense amplifier for reading non-volatile memory cells
    Patent number: 9460761
    Abstract: A sense amplifier includes: two detection inputs, a latch circuit including two sections coupled to each other and each supplying a data signal. Each section is respectively powered by a P-channel control transistor, having a gate terminal receiving a control signal linked to a respective detection input of the two detection inputs. The sense amplifier includes a control circuit configured to reduce each of the control signals to a sufficiently low voltage to put the corresponding control transistor to the on state, when the control signal reaches a reference voltage. The latch circuit is activated to supply one of the data signals when a corresponding one of the control transistors is in the on state.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 4, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francesco La Rosa
  • Memory cell having a vertical selection gate formed in an FDSOI substrate
    Patent number: 9461129
    Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: October 4, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Arnaud Regnier, Jean-Michel Mirabel, Stephan Niel, Francesco La Rosa
  • Method for programming a non-volatile memory cell comprising a shared select transistor gate
    Patent number: 9443598
    Abstract: The present disclosure relates to a method for controlling two twin memory cells each comprising a floating-gate transistor comprising a state control gate, in series with a select transistor comprising a select control gate common to the two memory cells, the drains of the floating-gate transistors being connected to a same bit line, the method comprising steps of programming the first memory cell by hot-electron injection, by applying a positive voltage to the bit line and a positive voltage to the state control gate of the first memory cell, and simultaneously, of applying to the state control gate of the second memory cell a positive voltage capable of causing a programming current to pass through the second memory cell, without switching it to a programmed state.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: September 13, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier