Abstract: Embodiments disclosed herein describe systems, methods, and products for safety verification of an IC design. A computer executing an illustrative EDA tool may perform a static cone of influence (COI) analysis of a gate-level netlist of the IC design to determine whether faults injected at combinational logic at different COIs are safe or dangerous. The computer may leverage this determination to perform a register-transfer level (RTL) simulation by generating and injecting equivalent faults to sequential logic in the IC design. The computer may further flexibly allow RTL simulations under different assumptions based upon downstream observability of the faults injected to the sequential logic. Because, RTL simulations are significantly faster than the gate-level simulations, the computer may efficiently calculate DC of one or more safety mechanism in the IC design.

Abstract: Devices, methods, non-transitory computer readable media, and other embodiments are described for automatic gate-level functional safety (FS) analysis and associated circuit design operations. One embodiment involves accessing register transfer level (RTL) design data, and accessing a set of FS data associated with an initial circuit design describing one or more failure modes associated with a plurality of circuit elements, an associated FS design criterion for each failure mode of the one or more failure modes, and one or more associations between the plurality of circuit elements and the one or more failure modes. The embodiment then involves generating a gate-level netlist using the RTL design data, mapping the one or more associations between the plurality of circuit elements from the RTL design data and the one or more failure modes to the gate-level netlist, and generating an updated set of FS data using the mapping of the one or more associations to the gate-level netlist.

Abstract: Integrated device comprising: a microprocessor unit (1) which is interfaced to a program memory unit (2), a data memory unit (3), one or more integrated sensors (11), one or more external sensors (12) which may be either digitally or analogically interfaced, an RFID unit (7, 107), an RTC (Real Time Clock) synchronization module (5, 105) which can also control power supply means (13), said device further comprising a power supply and consumption management logic.

Abstract: Taught is a detection device for detecting impacts and the like, comprising an integrated microcontroller (1) which includes an RFID interface (101) and a non-volatile memory (201), the integrated microcontroller (1) being interfaced with at least one suitable sensing means (2) through a suitable digital interface (102), the integrated microcontroller (1) being provided with a power management logic (301) to manage operation modes of the detection device, power consumption of the sensing means (2) being managed by the power management logic (301).

Abstract: A system-on-chip arrangement having, in possible combination with a processor, a plurality of reconfigurable gate array devices, and a configurable Network-on-Chip connecting the gate array devices to render the arrangement scalable. The arrangement lends itself to be operated by mapping in one device of the gate array a set of processing modules, and configuring another device of the plurality of gate array devices as a microcontroller having stored therein software code portions for controlling inter-operation of the processing modules stored in the one device of the plurality. The arrangement is thus adapted, e.g., to handle different computational granularity levels.

Abstract: A monitoring apparatus for tanks and the like, comprising detecting means (4; 506) to detect the filling level of a tank, detecting means (5, 106; 206) to detect the opened and closed states of opening/closing means (6) of said tank, and gathering and processing means (106) to gather and process the detected data, characterized in that said processing means (106) are integrated with an RFID unit (116) which can communicate said data with at least one appropriate remote transceiver unit (7).

Abstract: Integrated device comprising: a microprocessor unit (1) which is interfaced to a program memory unit (2), a data memory unit (3), one or more integrated sensors (11), one or more external sensors (12) which may be either digitally or analogically interfaced, an RFID unit (7, 107), an RTC (Real Time Clock) synchronization module (5, 105) which can also control power supply means (13), said device further comprising a power supply and consumption management logic.

Abstract: A monitoring apparatus for tanks and the like, comprising detecting means (4; 506) to detect the filling level of a tank, detecting means (5, 106; 206) to detect the opened and closed states of opening/closing means (6) of said tank, and gathering and processing means (106) to gather and process the detected data, characterized in that said processing means (106) are integrated with an RFID unit (116) which can communicate said data with at least one appropriate remote transceiver unit (7).

Abstract: A dynamically reconfigurable processing unit includes a microprocessor, and an embedded Flash memory for non-volatile storage of code, data and bit-streams. The embedded Flash includes a field programmable gate array (FPGA) port. The reconfigurable processing unit further includes a direct memory access (DMA) channel, and an S-RAM embedded FPGA for FPGA reconfigurations. The S-RAM embedded FPGA has an FPGA programming interface connected to the FPGA port of the Flash memory through the DMA channel. The microprocessor, the embedded Flash memory, the DMA channel and the S-RAM embedded FPGA are integrated as a single chip.

Abstract: Taught is a detection device for detecting impacts and the like, comprising an integrated microcontroller (1) which includes an RFID interface (101) and a non-volatile memory (201), the integrated microcontroller (1) being interfaced with at least one suitable sensing means (2) through a suitable digital interface (102), the integrated microcontroller (1) being provided with a power management logic (301) to manage operation modes of the detection device, power consumption of the sensing means (2) being managed by the power management logic (301).

Abstract: A system-on-chip arrangement having, in possible combination with a processor, a plurality of reconfigurable gate array devices, and a configurable Network-on-Chip connecting the gate array devices to render the arrangement scalable. The arrangement lends itself to be operated by mapping in one device of the gate array a set of processing modules, and configuring another device of the plurality of gate array devices as a microcontroller having stored therein software code portions for controlling inter-operation of the processing modules stored in the one device of the plurality. The arrangement is thus adapted, e.g., to handle different computational granularity levels.

Abstract: A dynamically reconfigurable processing unit includes a microprocessor, and an embedded Flash memory for non-volatile storage of code, data and bit-streams. The embedded Flash includes a field programmable gate array (FPGA) port. The reconfigurable processing unit further includes a direct memory access (DMA) channel, and an S-RAM embedded FPGA for FPGA reconfigurations. The S-RAM embedded FPGA has an FPGA programming interface connected to the FPGA port of the Flash memory through the DMA channel. The microprocessor, the embedded Flash memory, the DMA channel and the S-RAM embedded FPGA are integrated as a single chip.