Abstract: The invention relates to a device for controlling the phases of a charge pump 20, which device includes a phase generator 9 and a charge pump that is provided with a plurality of stages 1, 2. The invention also relates to a driver circuit for driving a display device with a charge pump and a phase generator, and to a display device with a driver circuit and a charge pump and a phase generator. In order to enable optimum adjustment of the delays between the individual phases P1 to P4 for the control of a charge pump and also to enable a response to disturbances that are caused by changes of the load or the temperature, signals 14 to 17 are fed back from the charge pump to a phase generator 9 so that the phases are started only when the appropriate conditions or states of the other phases exist.

Abstract: The invention relates to a device for controlling the phases of a charge pump 20, which device includes a phase generator 9 and a charge pump that is provided with a plurality of stages 1, 2. The invention also relates to a driver circuit for driving a display device with a charge pump and a phase generator, and to a display device with a driver circuit and a charge pump and a phase generator. In order to enable optimum adjustment of the delays between the individual phases P1 to P4 for the control of a charge pump and also to enable a response to disturbances that are caused by changes of the load or the temperature, signals 14 to 17 are fed back from the charge pump to a phase generator 9 so that the phases are started only when the appropriate conditions or states of the other phases exist.

Abstract: The invention relates to a voltage multiplier such as a charge pump circuit. The circuit is realized by a plurality of cascade connected voltage gain stages, each stage comprising a first and a second cell each receiving a pair of clock phase signals and comprising a pair of MOS transistors having first and second conduction terminals and a control terminal. These transistors have their first conduction terminals connected together and to a voltage reference; while the control terminals of each transistor are connected to the second conduction terminal of the other transistor of the same cell. Moreover, the second conduction terminal of the first transistor receives a first phase signal via a first coupling capacitor, and the second conduction terminal of the second transistor receives a second phase signals via a first pumping capacitor. Third and fourth cells are provided having the same structure as the first and the second cell.