Patents by Inventor Francesco Mammoliti

Francesco Mammoliti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Logical fuzzy union and intersection operation calculation circuit
    Patent number: 6862584
    Abstract: The calculation circuit comprises a subtracter having a first and a second input receiving a first and, respectively, a second input datum; a first output supplying a first output datum equal to the difference between the first and the second input datum; and a second output supplying a sign flag indicating the sign of the first output datum; an XOR logic gate having a first input receiving the sign flag, a second input receiving a first logic selection signal assuming a first level for the selection of the logical fuzzy union operation and a second level for the selection of the logical fuzzy intersection operation, and an output supplying a second logic selection signal; and a multiplexer having a first and a second datum input receiving the first and, respectively, the second input datum; a selection input receiving the second selection signal; and an output supplying a second output datum constituted by the first or the second input datum (A, B) as a function of the level assumed by the second selection s
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: March 1, 2005
    Assignee: STMicroelectronics S.r.l.
    Inventors: Francesco Pappalardo, Biagio Giacalone, Francesco Mammoliti, Edmondo Gangi
  • Logical fuzzy union and intersection operation calculation circuit
    Publication number: 20010039538
    Abstract: The calculation circuit comprises a subtracter having a first and a second input receiving a first and, respectively, a second input datum; a first output supplying a first output datum equal to the difference between the first and the second input datum; and a second output supplying a sign flag indicating the sign of the first output datum; an XOR logic gate having a first input receiving the sign flag, a second input receiving a first logic selection signal assuming a first level for the selection of the logical fuzzy union operation and a second level for the selection of the logical fuzzy intersection operation, and an output supplying a second logic selection signal; and a multiplexer having a first and a second datum input receiving the first and, respectively, the second input datum; a selection input receiving the second selection signal; and an output supplying a second output datum constituted by the first or the second input datum (A, B) as a function of the level assumed by the second selection s
    Type: Application
    Filed: November 29, 2000
    Publication date: November 8, 2001
    Inventors: Francesco Pappalardo, Biagio Giacalone, Francesco Mammoliti, Edmondo Gangi