Abstract: Apparatus (40) comprising a plurality of output buffers (41.1-41.N) for driving the columns of an LCD panel (46). A bias generator (42) is employed for providing a common biasing current (Ibias) to all output buffers (41.1-41.N). Means (43) provide information regarding the physical position of a dot to be driven on the LCD panel (46) by counting the number of incoming load signals (LD). A switchable current source (42) changes the level of the biasing current (Ibias) according to the physical position.

Abstract: The invention relates to a comparator with a constant duty cycle for high frequency data signals. Such comparators are often part of an integrated circuit and particularly useful in the mobile phone technology. To achieve the desired constant duty cycle for high frequency data signals, the comparator according to the invention comprises a differential amplifier (M1, M2) having differential inputs (IN 1, IN2) forming the comparator inputs and a first and second amplifier output (Vo, Vo?) forming the comparator outputs of a first comparator stage. Further, a first differential current amplifier (A11) is provided and connected with its inputs to the amplifier outputs (Vo, Vo?) and with its output to the first amplifier output (Vo). Finally, a second differential current amplifier (A12) is connected with its inputs to the amplifier outputs (Vo, Vo?) and with its output to the second amplifier output (Vo?).

Abstract: Apparatus (40) comprising a plurality of output buffers (41.1-41.N) for driving the columns of an LCD panel (46). A bias generator (42) is employed for providing a common biasing current (Ibias) to all output buffers (41.1-41.N). Means (43) provide information regarding the physical position of a dot to be driven on the LCD panel (46) by counting the number of incoming load signals (LD). A switchable current source (42) changes the level of the biasing current (Ibias) according to the physical position.

Abstract: The invention concerns a circuit arrangement (2) for driving a display arrangement (1). Further it concerns a display arrangement (1) and a method for driving a display arrangement (1). To provide an arrangement (2) having a good offset cancellation combined with high quality illustrating of an image the circuit arrangement includes column driving means (5) for driving n column electrodes (C) and row driving means (4) for driving m row electrodes (R) of the display arrangement (1), wherein the column driving means (5) comprises n output channels (O), each output channel (O) having a column electrode (C) assigned and is arranged for providing a respective column voltage to the assigned column electrode (C), an additional output channel (OR) is arranged for providing a respective column voltage, whereas each of the n column electrodes (C) is connectable to the additional output channel (OR). The additional output channel (OR) will be calibrated at first.

Abstract: The invention relates to a comparator with a constant duty cycle for high frequency data signals. Such comparators are often part of an integrated circuit and particularly useful in the mobile phone technology. To achieve the desired constant duty cycle for high frequency data signals, the comparator according to the invention comprises a differential amplifier (M1, M2) having differential inputs (IN 1, IN2) forming the comparator inputs and a first and second amplifier output (Vo, Vo?) forming the comparator outputs of a first comparator stage. Further, a first differential current amplifier (A11) is provided and connected with its inputs to the amplifier outputs (Vo, Vo?) and with its output to the first amplifier output (Vo). Finally, a second differential current amplifier (A12) is connected with its inputs to the amplifier outputs (Vo, Vo?) and with its output to the second amplifier output (Vo?).

Abstract: Apparatus (50) for processing a differential input signal. The apparatus (50) comprises a minimum peak detector (51) with a differential input (28). The peak detector (51) provides a first voltage being proportional to an average voltage peak at the peak detector's differential input (28). A compressor (53) is provided for processing the first voltage in order to provide a second voltage. The compressor (53) is followed by a voltage controllable current source providing a trim current that is adjustable by the second voltage. A hysteresis equipped circuit (67.1) whose hysteresis characteristics are adjustable by the trim current is part of the apparatus (50).

Abstract: An interface manages the exchange of information between a bus system and a memory during reading, according to a communication protocol. The interface has a protocol-decoding unit, which receives from outside commands and information for managing the reading and generates a wait-code enabling signal, and a wait-state generating unit, which is connected to the protocol-decoding unit and outputs wait codes upon receipt of the wait-code enabling signal. When the memory ends reading, as signaled by switching of a read-state signal, a wait-state disabling circuit generates and supplies an end-of-waiting control signal to the wait-state generating unit, which thus outputs an end-of-waiting code.

Abstract: The reading timing device has a data-sensing stage, receiving a sensing-latch signal, and an output stage, including an output buffer and enabled at a first switching edge of a synchronization signal. A reading timing stage generates the sensing-latch signal not before a preset time interval from the first switching edge of the synchronization signal. Thereby, reading, in particular data-latching in the data-sensing stage, is temporarily separated from switching of the output buffers. This separation is obtained using the sync signal. Since the output buffers must switch in a preset time from the rising edge of the sync signal, the pulse of the sensing-latch signal is shifted after this time, and more precisely after the falling edge of the sync signal.

Abstract: An interface manages the exchange of information between a bus system and a memory during reading, according to a communication protocol. The interface has a protocol-decoding unit, which receives from outside commands and information for managing the reading and generates a wait-code enabling signal, and a wait-state generating unit, which is connected to the protocol-decoding unit and outputs wait codes upon receipt of the wait-code enabling signal. When the memory ends reading, as signaled by switching of a read-state signal, a wait-state disabling circuit generates and supplies an end-of-waiting control signal to the wait-state generating unit, which thus outputs an end-of-waiting code.

Abstract: The reading timing device has a data-sensing stage, receiving a sensing-latch signal, and an output stage, including an output buffer and enabled at a first switching edge of a synchronization signal. A reading timing stage generates the sensing-latch signal not before a preset time interval from the first switching edge of the synchronization signal. Thereby, reading, in particular data-latching in the data-sensing stage, is temporarily separated from switching of the output buffers. This separation is obtained using the sync signal. Since the output buffers must switch in a preset time from the rising edge of the sync signal, the pulse of the sensing-latch signal is shifted after this time, and more precisely after the falling edge of the sync signal.