Abstract: A plurality of binary counters, each consisting of a primary and a secondary counting chain, are stepped by respective trains of clock pulses of like cadence but indeterminate phase relationship. The several primary counting chains are provided on their input sides with respective correlation circuits and on their output sides with respective sync generators, either of which is used for a concurrent restarting of both chains upon the attainment of a full count. A selection signal establishes one of the primary counting chains as the master by unblocking its sync generator while blocking its correlation circuit, the opposite being the case in all the other counters which are controlled from the unblocked sync generator through their respective correlation circuits.

Abstract: Three or more oscillators to be locked in phase with one another are interconnected in a closed ring and have individual feedback loops including respective frequency dividers designed to keep them in step with a synchronizing frequency, equal to a fraction of their own operating frequency, fed in through an associated multiplexer. The multiplexer has a first input receiving the stepped-down feedback frequency of the immediately preceding oscillator, a second input connected to the output of the associated frequency divider, and a third input energizable with an external reference frequency such as a carrier of a PCM of FDM system. Each multiplexer, in the absence of an external switching command which holds it on its third input, stands on its first input unless a control circuit associated with the immediately preceding oscillator detects a disparity between the two frequencies fed to that preceding oscillator via the feedback loop and the multiplexer of the latter.