Abstract: Pulse formers (14) driving respective LEDs (12) are energized by the cells of a shift register (16) which is docked by a clock line (CK), and to whose first cell an initial pulse is applied by a first signal generator (GR). A barrier-end Line (FB) is connected to the output of the shift register and to the input of the first signal generator. The latter resets the shift register cells through a reset line (RS). A plurality of photodiodes (42) facing the LEDs are connected in common to a bus line (BUS) through resistors (47) and electronic switches (44) which are dosed in turn by the cells of a shift register (46) similarly controlled by a second signal generator (GE) in synchronism with the first. The bus line is connected across a voltage supply through resistors (61, 63) and provides a multi-level signal to an evaluator circuit (VAL). The two shift registers, including the associated LEDs or photodiodes, may form blocks connected in cascade.