Abstract: A method is for the identification of an integrated circuit, and includes steps for writing, in a volatile register, a required number; the decoding, in the integrated circuit, of the required number and the reading of the identification number if the integrated circuit is not compatible with the required circuit or the reading of the required number if the integrated circuit is compatible with the required circuit. An identification device may include a non-volatile register, a volatile register, a decoder and a router.

Abstract: The present invention relates to a device for receiving digital signals including a decoding device for generating p bits from q received signals, p and q being integers such that p is less than or equal to q, one bit of the p bits being generated from an integer number n of received signals, the decoding device including at least one signal processing circuit, the operation of which is clocked by a first clock signal having a frequency which depends on the frequency of reception of the signals received and at least one logic data processing circuit, the operation of which depends on both the receive frequency of the signals received and the number of signals necessary to generate a given bit, including circuitry for generating a second clock signal to clock the operation of the data processing circuit, this circuitry being constructed and arranged so that the second clock signal has a frequency equal to the receive frequency of the received signals and is active or inactive according to the number of receive

Abstract: The present invention relates to a circuit for removing energy dispersal in the transmission of a data packet, the circuit including a polynomial counter for supplying, at the transmission rate of the bits of the packet, correction bits to be respectively X-ORed with the bits of the packet. The correction bits are supplied to a series-to-parallel converter having its output combined with the successive packet parallel transmitted bits of the packet.