Abstract: An adaptive lossless data compression method for compression of color image data in a data processing system. The method includes comparing a plurality of components of a plurality of adjacent pixels in a digital image, calculating spatial differences between the plurality of adjacent pixels, encoding the spatial differences and recording the encoded spatial differences, formatting an image file representing the digital image into byte streams based on bit significance, and compressing, independently, the byte streams associated with each bit significance of the encoded spatial differences.

Abstract: A method for simulating a circuit. The method includes, in response to a first mode change triggering event at a first time point and in response to a first data transfer triggering event at a second time point after the first time point, generating a random value of at least a first random value and a second random value. In response to the generated random value being the first random value, a first input value of an input of the circuit is assigned to an output of the circuit. In response to the generated random value being the second random value, an output value of the output of the circuit is maintained. In response to a second data transfer triggering event at a third time point after the second time point, a second input value of the input of the circuit is assigned to the output of the circuit.

Abstract: Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

Abstract: The invention generally relates to design verification, and more particularly to verification of non-deterministic behavior of a design under test. A method includes predicting a plurality of behaviors of a design under test (DUT), and forking respective verification tasks for each one of the plurality of behaviors. The method further includes verifying an actual behavior of the DUT with each of the verification tasks, and terminating a respective one of the verification tasks when the actual behavior of the DUT does not conform to the respective one of the verification tasks.

Abstract: A solution for generating functional coverage bins for testing a device is disclosed. A method includes: receiving information of a failing test generated from a random simulation performed on the device; tracing a first sequence of signal events that happened in the failing test; correlating the signal events to coverage bins to generate a sequence of coverage bins; creating cross coverage event sequence bins based on the sequence of coverage bins; and outputting the created coverage event sequence bins for testing the device.

Abstract: A method for simulating a circuit. The method includes, in response to a first mode change triggering event at a first time point and in response to a first data transfer triggering event at a second time point after the first time point, generating a random value of at least a first random value and a second random value. In response to the generated random value being the first random value, a first input value of an input of the circuit is assigned to an output of the circuit. In response to the generated random value being the second random value, an output value of the output of the circuit is maintained. In response to a second data transfer triggering event at a third time point after the second time point, a second input value of the input of the circuit is assigned to the output of the circuit.

Abstract: An adaptive lossless data compression method for compression of color image data in a data processing system. The method includes comparing a plurality of components of a plurality of adjacent pixels in a digital image, calculating spatial differences between the plurality of adjacent pixels, encoding the spatial differences and recording the encoded spatial differences, formatting an image file representing the digital image into byte streams based on bit significance, and compressing, independently, the byte streams associated with each bit significance of the encoded spatial differences.

Abstract: A solution for generating functional coverage bins for testing a device is disclosed. A method includes: receiving information of a failing test generated from a random simulation performed on the device; tracing a first sequence of signal events that happened in the failing test; correlating the signal events to coverage bins to generate a sequence of coverage bins; creating cross coverage event sequence bins based on the sequence of coverage bins; and outputting the created coverage event sequence bins for testing the device.

Abstract: The invention generally relates to design verification, and more particularly to verification of non-deterministic behavior of a design under test. A method includes predicting a plurality of behaviors of a design under test (DUT), and forking respective verification tasks for each one of the plurality of behaviors. The method further includes verifying an actual behavior of the DUT with each of the verification tasks, and terminating a respective one of the verification tasks when the actual behavior of the DUT does not conform to the respective one of the verification tasks.

Abstract: A digital circuit simulation method. The method starts with a digital circuit design which includes: a first source latch, a destination latch, a logic cone, a first WAM circuit electrically coupling an output of the first source latch to a first input of the logic cone, and a WAGG circuit electrically coupling an output of the logic cone and an input of the first source latch. Then, a zero-delay simulation is performed in which if a first situation of (a) the first WAM circuit entering an uncertainty state in which the first WAM circuit generates a random value of 1 or 0 at the first input of the logic cone, (b) the logic cone being vulnerable to a positive glitch, and (c) the output of the logic cone being at logic 0, the WAGG circuit generates a random value of 0 or 1 at the input of the destination latch.

Abstract: Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

Abstract: Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

Abstract: An optical transmission method. Signal transmissions between cores of an integrated circuit are performed. Each signal transmission is between two cores of a different pair of cores of the integrated circuit. Each signal transmission includes transmission of an optical signal in the visible or infrared portion of the electromagnetic spectrum at a wavelength that is specific to each different pair of cores and is a different wavelength for each different pair of cores. There is no overhead for decoding or arbitration in preforming the signal transmissions that would otherwise exist if a same wavelength for the optical signals were permitted for pairs of cores of the different pairs of cores.

Abstract: A method, apparatus, and computer program product for performing verification on an integrated circuit design having state variables. Random vectors are generated, used to simulate the design, and generate a set of values for the state variables. The generated values are compared to groups having stored values from previous stimulations and either a new group is created for the generated set of values or the existing groups accurately represent the generated set of values and they are stored in one of the existing groups.

Abstract: A digital circuit simulation method. The method starts with a digital circuit design which includes: a first source latch, a destination latch, a logic cone, a first WAM circuit electrically coupling an output of the first source latch to a first input of the logic cone, and a WAGG circuit electrically coupling an output of the logic cone and an input of the first source latch. Then, a zero-delay simulation is performed in which if a first situation of (a) the first WAM circuit entering an uncertainty state in which the first WAM circuit generates a random value of 1 or 0 at the first input of the logic cone, (b) the logic cone being vulnerable to a positive glitch, and (c) the output of the logic cone being at logic 0, the WAGG circuit generates a random value of 0 or 1 at input of the destination latch.

Abstract: Disclosed is an integrated circuit comprising a plurality of cores attached to at least one transmitter and receiver, an optical transmission network embedded within the wire levels of the integrated circuit, and wherein the transmitter and receivers send and receive data on the network. Also disclosed is a method of transmitting signals within an integrated circuit comprising an integrated circuit comprising a plurality of cores and optical paths, selecting an optical path from the plurality of optical paths for transmitting data, and transmitting the data on the selected optical path. Also disclosed is an integrated circuit comprising an optical transmission network, a plurality of cores, and a plurality of controllers, all three being operatively attached to each other.

Abstract: A method, apparatus, and computer program product for performing verification on an integrated circuit design having state variables. Random vectors are generated, used to simulate the design, and generate a set of values for the state variables. The generated values are compared to groups having stored values from previous stimulations and either a new group is crated for the generated set of values or the existing groups accurately represent the generated set of values and they are stored in one of the existing groups.

Abstract: A method and system for testing a circuit design. The method including generating a simulation model of the circuit design, the circuit design comprising one or more source latches, one or more destination latches and a logic function connected between the source latches and the destination latches; generating a modified simulation model of the simulation model by inserting random skew between an output of each source latch and an input of the logic function only in asynchronous data paths between the source latches and the destination latches of the simulation model; and running the modified simulation model.

Abstract: Embodiments herein present a method for automated simulation testbench generation for serializer/deserializer datapath systems. The method provides a database of transactors for generating and checking data within the datapath system, wherein the transactors are adaptable to arbitrary configurations of the datapath system. The database is provided with a single set of transactors per core. Next, the method automatically selects one set of transactors from the database for inclusion into the simulation testbenches. Following this, the method maps the first datapath and the second datapath through the datapath system by interconnecting the selected set of the transactors with the datapath system. The method further comprises setting control pins on the cores to facilitate propagation of the data through the cores of the datapath system. Subsequently, the control pins are traced to input ports and control registers.

Abstract: Thread entries are stored in a memory of the system to indicate executed instruction threads. Uses of processing resources by the respective instruction threads are detected and history entries for the threads are stored in a memory of the system. Such history entries indicate whether respective processing resources have been used by respective ones of the instruction threads. The history entries of first and second ones of the instruction threads are compared. The second instruction thread is selected for executing if the comparing indicates history of processing resources used by the first thread has a certain difference relative to history of processing resources used by the second thread.