Abstract: Gas switching is used during an etch process to modulate the characteristics of the etch. The etch process comprises a sequence of at least three steps, wherein the sequence is repeated at least once. For example, the first step may result in a high etch rate of oxide (108) while the second step is a polymer coating steps and the third step results in a low etch rate of oxide and high etch rate of another material (114) and/or sputtering.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: Gas switching is used during an etch process to modulate the characteristics of the etch. The etch process comprises a sequence of at least three steps, wherein the sequence is repeated at least once. For example, the first step may result in a high etch rate of oxide (108) while the second step is a polymer coating steps and the third step results in a low etch rate of oxide and high etch rate of another material (114) and/or sputtering.

Abstract: Gas switching is used during an etch process to modulate the characteristics of the etch. The etch process comprises a sequence of at least three steps, wherein the sequence is repeated at least once. For example, the first step may result in a high etch rate of oxide (108) while the second step is a polymer coating steps and the third step results in a low etch rate of oxide and high etch rate of another material (114) and/or sputtering.

Abstract: Gas switching is used during an etch process to modulate the characteristics of the etch. The etch process comprises a sequence of at least three steps, wherein the sequence is repeated at least once. For example, the first step may result in a high etch rate of oxide (108) while the second step is a polymer coating steps and the third step results in a low etch rate of oxide and high etch rate of another material (114) and/or sputtering.

Abstract: A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched to form an etched barrier layer (205), and etched first metal layer (215), and etched ferroelectric layer (225), and etched second metal layers (235, 245). The etched layers form a ferroelectric memory capacitor (270) with sidewalls that form an angle with the plane of the upper surface of the dielectric layer (70) between 78° and 88°. The processes used to etch the layers are plasma processes performed at temperatures between 200° C. and 500° C.

Abstract: A method of patterning a polysilicon feature includes forming a hard mask layer over a polysilicon layer, wherein the hard mask layer includes a silicon rich silicon oxynitride layer, and a silicon oxynitride layer or bottom anti-reflective coating (BARC) layer overlying the silicon rich silicon oxynitride layer. The method further includes forming a photoresist layer over the hard mask layer, selectively exposing the photoresist layer with 193 nm ultraviolet radiation, and developing the exposed photoresist, thereby defining a photoresist feature. The hard mask layer is then patterned using the photoresist feature as an etch mask, and the polysilicon layer is patterned using the patterned hard mask as an etch mask.

Abstract: A method of manufacturing a semiconductor device by qualifying an etch process. A semiconductor substrate is subjected to a predefined etch process to produce a partially-etched film. A scatterometry signature of the partially-etched film is produced. The scatterometry signature is used to determine if a physical property of the partially-etched film matches a target result.

Abstract: A method of forming a gate electrode (24?) for a metal-oxide-semiconductor (MOS) integrated circuit is disclosed. A hardmask layer (26), for example formed of silicon-rich nitride, is deposited over a polysilicon layer (24) from which the gate electrode (24?) is to be formed. An anti-reflective coating, or bottom anti-reflective coating or BARC, layer (29) is then formed over the hardmask layer (26), and photoresist (30) is photolithographically patterned to define the pattern of the gate electrode (24?), although to a wider, photolithographic, width (LW). The pattern is transferred from the photoresist (30) to the BARC layer (29). The remaining elements of the BARC layer (29) are then trimmed, preferably by a timed isotropic etch, to a sub-lithographic width (SW). This pattern is then transferred to the hardmask layer (26) by an anisotropic etch of that layer, using the trimmed BARC elements (29) as a mask.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.

Abstract: The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.