Patents by Inventor Francis Chapman
Francis Chapman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8776408Abstract: The present invention provides a protective shroud assembly for use on a wear edge of earthmoving machinery. The shroud assembly comprises a shroud adapted to be received with respect to the wear edge. The shroud has a wear region at a second end thereof which is adapted to engage the earth as the wear edge moves therethrough. The shroud assembly also comprises a locking means having a portion which is rotatably received in the shroud such that the shroud is releasably secured with respect to the wear edge when the locking means is in a locked position.Type: GrantFiled: August 25, 2008Date of Patent: July 15, 2014Assignees: Wearforce Pty Ltd, Castech Solutions Pty Ltd, Daxit Pty LtdInventor: Amy Francis Chapman
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Patent number: 8212332Abstract: A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip. The deep penetration of the capacitor creates a grounded shield deep in the substrate as compared with other prior art shielding techniques.Type: GrantFiled: August 11, 2011Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: Phillip Francis Chapman, David Goren, Rajendran Krishnasamy, Benny Sheinman, Shlomo Shlafman, Raminderpal Singh, Wayne H. Woods
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Publication number: 20110291238Abstract: A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip.Type: ApplicationFiled: August 11, 2011Publication date: December 1, 2011Applicant: International Business Machines CorporationInventors: Phillip Francis Chapman, David Goren, Rajendran Krishnasamy, Benny Sheinman, Shlomo Shlafman, Raminderpal Singh, Wayne H. Woods
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Patent number: 8021941Abstract: A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip. The deep penetration of the capacitor creates a grounded shield deep in the substrate as compared with other prior art shielding techniques.Type: GrantFiled: July 21, 2009Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Phillip Francis Chapman, David Goren, Rajendran Krishnasamy, Benny Sheinman, Shlomo Shlafman, Raminderpal Singh, Wayne H. Woods
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Publication number: 20110018094Abstract: A novel and useful apparatus for and method of providing noise isolation between integrated circuit devices on a semiconductor chip. The invention addresses the problem of noise generated by digital switching devices in an integrated circuit chip that may couple through the silicon substrate into sensitive analog circuits (e.g., PLLs, transceivers, ADCs, etc.) causing a significant degradation in performance of the sensitive analog circuits. The invention utilizes a deep trench capacitor (DTCAP) device connected to ground to isolate victim circuits from aggressor noise sources on the same integrated circuit chip.Type: ApplicationFiled: July 21, 2009Publication date: January 27, 2011Applicant: International Business Machines CorporationInventors: Phillip Francis Chapman, David Goren, Rajendran Krishnasamy, Benny Sheinman, Shlomo Shlafman, Raminderpal Singh, Wayne H. Woods
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Patent number: 7855420Abstract: A design structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits.Type: GrantFiled: March 6, 2008Date of Patent: December 21, 2010Assignee: International Business Machines CorporationInventors: Phillip Francis Chapman, David S. Collins, Steven H. Voldman
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Patent number: 7741681Abstract: A structure and a method for preventing latchup. The structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits.Type: GrantFiled: December 14, 2007Date of Patent: June 22, 2010Assignee: International Business Machines CorporationInventors: Phillip Francis Chapman, David S. Collins, Steven H. Voldman
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Patent number: 7696541Abstract: A structure, method and a design structure for preventing latchup in a gate array. The design structure including: a NFET gate array and a PFET gate array in a substrate; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate the NFET gate array and PFET gate array, the through via electrically contacting the P-well.Type: GrantFiled: March 6, 2008Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventors: Phillip Francis Chapman, David S. Collins, Steven H. Voldman
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Publication number: 20090205227Abstract: The present invention provides a protective shroud assembly for use on a wear edge of earthmoving machinery. The shroud assembly comprises a shroud adapted to be received with respect to the wear edge. The shroud has a wear region at a second end thereof which is adapted to engage the earth as the wear edge moves therethrough. The shroud assembly also comprises a locking means having a portion which is rotatably received in the shroud such that the shroud is releasably secured with respect to the wear edge when the locking means is in a locked position.Type: ApplicationFiled: August 25, 2008Publication date: August 20, 2009Applicants: Wearforce Pty Ltd, Castech Solutions Pty Ltd, Daxit Pty LtdInventors: Danny Stewart, Amy Francis Chapman
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Publication number: 20090152632Abstract: A structure and a method for preventing latchup. The structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits.Type: ApplicationFiled: December 14, 2007Publication date: June 18, 2009Inventors: Phillip Francis Chapman, David S. Collins, Steven H. Voldman
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Publication number: 20090152593Abstract: A structure, method and a design structure for preventing latchup in a gate array. The design structure including: a NFET gate array and a PFET gate array in a substrate; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate the NFET gate array and PFET gate array, the through via electrically contacting the P-well.Type: ApplicationFiled: March 6, 2008Publication date: June 18, 2009Inventors: Phillip Francis Chapman, David S. Collins, Steven H. Voldman
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Publication number: 20090152592Abstract: A design structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits.Type: ApplicationFiled: March 6, 2008Publication date: June 18, 2009Inventors: Phillip Francis Chapman, David S. Collins, Steven H. Voldman
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Patent number: 7498622Abstract: A structure and a method for preventing latchup in a gate array. The structure including: a NFET gate array and a PFET gate array in a substrate; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate the NFET gate array and PFET gate array, the through via electrically contacting the P-well.Type: GrantFiled: December 14, 2007Date of Patent: March 3, 2009Assignee: International Business Machines CorporationInventors: Phillip Francis Chapman, David S. Collins, Steven H. Voldman
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Publication number: 20050061342Abstract: A press-on nail polish device comprises a conformable thin plastic element having an area and shape approximating the area and shape of a nail. The thin element has an adhesive of a strength to firmly hold the element to a nail, but to enable the element to be peeled away from a nail when desired. A kit comprises a plurality of the thin elements in contact with one release backing. A plurality of the release backings can be provided along with an emery board, orange stick and alcohol wipes.Type: ApplicationFiled: January 21, 2004Publication date: March 24, 2005Inventor: Francis Chapman
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Patent number: D569110Type: GrantFiled: October 26, 2007Date of Patent: May 20, 2008Inventors: Robert Francis Chapman, Wallace Daniel Chapman