Abstract: A memory system is disclosed, including a memory component and a processing device configured to decode one or more codewords saved to a memory region of the memory component, detect that a number of bit errors corresponding to the decoding of the codeword exceeds a correction capability of the processing device, and execute an error recovery routine to reduce the number of detected bit errors to within the correction capability. The error recovery routine can include error recovery operations that are sequentially executed either until the number of bit errors is successfully reduced to within the correction capability or until a set of the error recovery operations has been executed. The error recovery operations can be ordered according to one or more factors, including energy used to execute a respective error recovery operation, a duration of the respective operation, and/or a likelihood of success of the respective operation.

Abstract: A memory system can identify target memory units to characterize by generating Cumulative Distribution Function (CDF)-based data for each memory unit and analyzing the CDF-based data to identify target memory units that are exceptional. Such target memory units can be those with CDF-based data with extrinsic tails or that crosses an info limit threshold. The memory system can perform characterization processes for the target memory units, e.g. using an Auto Read Calibration (ARC) analysis or a Continuous Read Level Calibration (cRLC) analysis. A manufacturing process for the memory device can use results of the characterization processes, e.g. by mapping them to types of problems observed during testing. Alternatively, results of the characterization processes to can be used during operation of the memory device, e.g. to adjust the initial read voltage threshold, the read retry voltage values, or the order of read retry voltages used in data recovery.

Abstract: Several embodiments of memory devices and systems for real time block failure analysis are disclosed herein. In one embodiment, a system includes a memory array including a plurality of memory cells and a processing device coupled to the memory array. The processing device is configured to sense, in response to detection of an error associated with a subset of a plurality of memory cells of the memory device, a state associated with each memory cell of the subset of the plurality of memory cells. The processing device is further configured to store state distribution information in a persistent memory, the state distribution information comprising the sensed state associated with each memory cell of the subset.

Abstract: A memory device includes a memory device comprising a plurality of memory cells; and a processing device coupled to the memory device, the processing device configured to: determine at least one real-time measure including at least one environmental parameter or at least one operational parameter, or a combination thereof, wherein: the environmental parameter corresponds to one or more physical conditions concerning the system, the operational parameter represents one or more operations performed by the system; and generate an adjusted sampling rate based on the real-time measure, wherein the adjusted sampling rate replaces a previous sampling rate used to control a timing associated with gathering information for a sampling process.

Abstract: A system and method for storing data in multiple locations on the basis of rules maintained by the system. The invention can enable data management, collaboration of data usage between users and the storage of data. The invention can be used for just-in-time location, retrieval, aggregation and delivery of a view of information that may not result in the information being moved from or stored other than from the approved location. Optionally, further assurance of data location may be periodically provided by a location audit service.