Abstract: The present invention is a controller for producing a dual port function from a single port memory with an improved memory cycle time. An address or control signal transition for one port generates an access request signal for that port. The access request signal both (1) blocks an access request by the other port for its duration and (2) generates a series of signals for a memory access for the selected port. A multiplexer for providing addresses to the memory core from two ports is switched to select a second port while a first port access is in progress. The output of the multiplexer is not enabled until the memory core access is completed. Thus, the set-up time for the second set of addresses is allowed to overlap the memory core access time for the first set of addresses thereby reducing overall cycle time.