Abstract: An inductive coupling reader includes a passive interface circuit for modulating the impedance of an antenna circuit and extracting from the antenna circuit a data signal and a RF clock signal, and circuitry for coupling the reader to a removable security module. The reader includes an emulation circuit for opening a RF transmission channel with another reader, a non-removable electrical link linking the emulation circuit to the passive interface circuit, by which the data signal and the RF clock signal are supplied to the emulation circuit, and a data bus clocked by a bus clock signal having a frequency inferior to the frequency of the RF clock signal, for linking the emulation circuit to the removable security module. The reader has low electrical consumption.

Abstract: A method is provided for manufacturing an integrated electronic component arranged on a substrate wafer. According to the method, at least one metallization step is performed, and a value of an electrical parameter of the integrated electronic component is determined after the at least one metallization step. A subsequent metallization step is performed after determining the value of the electrical parameter. The subsequent metallization step is performed using an adjustment mask chosen from n predefined masks based on a desired value of the electrical parameter, so as to obtain the desired value of the electrical parameter of the integrated electronic component after manufacturing. In one preferred embodiment, a series of electrical tests is performed on the wafer using test equipment, and the value of the electrical parameter is determined using the same test equipment as is used to perform the series of electrical tests.

Abstract: An inductive coupling reader includes a passive interface circuit for modulating the impedance of an antenna circuit and extracting from the antenna circuit a data signal and a RF clock signal, and circuitry for coupling the reader to a removable security module. The reader includes an emulation circuit for opening a RF transmission channel with another reader, a non-removable electrical link linking the emulation circuit to the passive interface circuit, by which the data signal and the RF clock signal are supplied to the emulation circuit, and a data bus clocked by a bus clock signal having a frequency inferior to the frequency of the RF clock signal, for linking the emulation circuit to the removable security module. The reader has low electrical consumption.

Abstract: The invention concerns a demodulator of an amplitude-modulated signal (Vdb), characterised in that it comprises a peak detecting cell (DCR) capable of extracting the reference modulating signal (Vpeak1) of the modulated signal (Vdb); a first demodulator (FE) adapted to detect the peak of the reference modulating signal (Vpeak1) to generate a high comparison threshold and locate the start of the modulation, a second demodulator (RE) adapted to detect a trough of the reference modulating signal (Vpeak1) to generate a low comparison threshold and locate the end of the modulation; a logic processing unit capable of supplying the demodulated signal (Vdemod).

Abstract: The invention concerns a method for making an integrated electronic component arranged on a substrate wafer comprising at least two met allising steps. The invention is characterised in that the value of an electrical parameter of the component is determined after a metallising step, and one of the following metallising processes is carried out with an adjusting mask selected among n predefined masks to obtain a desired value of the parameter, the selection of the adjusting mask being performed in accordance with the predetermined value of the electrical parameter.

Abstract: The invention concerns a demodulator of an amplitude-modulated signal (Vdb), characterised in that it comprises a peak detecting cell (DCR) capable of extracting the reference modulating signal (Vpeak1) of the modulated signal (Vdb); a first demodulator (FE) adapted to detect the peak of the reference modulating signal (Vpeak1) to generate a high comparison threshold and locate the start of the modulation, a second demodulator (RE) adapted to detect a trough of the reference modulating signal (Vpeak1) to generate a low comparison threshold and locate the end of the modulation; a logic processing unit capable of supplying the demodulated signal (Vdemod).

Abstract: A current amplifier includes a cascode transistor for fixing the voltage of an input of the amplifier; a first constant current source connected between the input and a first supply voltage; a second constant current source, for providing a current lower than the first current source, connected between a second supply voltage and the cascode transistor; a second transistor, of different type than the cascode transistor, connected between the input and the second supply voltage, and controlled by the node between the cascode transistor and the second current source; and an output transistor of same type as the second transistor, connected to the second supply voltage and controlled by the node.

Abstract: The period of an input signal is subdivided into N parts by carrying out a count, during this period, of the pulses delivered by a clock. This number is divided by N and then the remainder of this division is distributed among all the N parts of the period of the input signal. This technique may be applied to the generation of scanning signals in television.

Abstract: A digital sample filtering device comprising storage device including ROM and RAM memory for storing in an interlaced manner, coefficients of at least two filters along with for each coefficient, data indicating to which of the filters the each coefficient belongs; a multiplier for multiplying at least one of the coefficients by a sample and an accumulator for adding the partial sums of the multiplication results for each of the filters.

Abstract: An digital-analog converter uses at least 2.sup.N -1 identical current sources capable of being calibrated to convert a number encoded on N bits and an additional current source designed to replace one of the 2.sup.N -1 current sources during the calibration of one of said sources. The additional current source is connected to the output by means of a sole additional commutator.

Abstract: A current amplifier includes a cascode transistor for fixing the voltage of an input of the amplifier; a first constant current source connected between the input and a first supply voltage; a second constant current source, for providing a current lower than the first current source, connected between a second supply voltage and the cascode transistor; a second transistor, of different type than the cascode transistor, connected between the input and the second supply voltage, and controlled by the node between the cascode transistor and the second current source; and an output transistor of same type as the second transistor, connected to the second supply voltage and controlled by the node.

Abstract: A digital-to-analog converter that includes pairs of positive and negative current sources that are connected through switches to two differential output lines. The switches are controlled as a function of a digital data. Each pair of current sources includes a pair of transistors of an output stage of a transconductance amplifier. The transconductance amplifier receives a reference voltage at a non-inverting input, and receives at an inverting input, the voltage at the middle node of a bridge of resistors that is connected between the two differential out-put lines. The output of the converter is the voltage between the two differential output lines.

Abstract: The disclosure is an analog-to-digital converter of half-flash type providing for the multiplexing of two analog input signals and therefore requiring only one converter module. It includes a coarse comparator block used to determine the most significant bits of the converted signals and also determining the voltage range for two fine comparator blocks that determine the least significant bits of the converted signals, wherein each of the input signals is connected to a fine comparator block and said coarse comparator block compares alternatively the first and second input signals with a reference voltage. The analog-to-digital converter can be advantageously used for processing television signals.

Abstract: The disclosure concerns a so-called "auto-zeroing" comparator of two analog input voltages to be compared, and an analog-to-digital converter using a set of auto-zeroing comparators enabling the number of comparators required for an analog-to-digital conversion to be reduced. The main originality of the invention is that this comparator includes a second stage constituted by an inverter function provided in such a way that only a first transistor is controlled on its gate by the previous stage, a second transistor having its gate and drain short-circuited by a switch during the auto-zeroing phase, and a third transistor used as a capacitor and connected to the gate of said second transistor and also to the supply voltage. The present invention is applicable in particular to all types of CMOS multi-comparison ADCs using at least one "auto-zeroing" comparator.

Abstract: The present invention relates to a method of enhancing the noise Immunity of a phase-locked loop. The phase-locked loop includes a comparator and apparatus for inhibiting the action of the comparator on the phase-locked loop. According to the method, the inhibition is lifted during a main time window resulting from the intersection of a first time window derived from the input signal of the phase-locked loop, and of a second time window derived from the loop-return signal.

Abstract: A phase detector of a phase-lock-loop circuit measures a phase error between an output signal of an oscillator and a synchronizing signal. When a difference between the phase error that is measured in a pair of horizontal line periods exceeds a first magnitude, that is indicative of phase error inconsistency, the phase of the oscillator output signal is not corrected and the phase-lock-loop circuit operates in an idle mode of operation.